Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 407
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
8. All user-design RTL files and constraints files (XDC files) can be viewed in the Sources >
Libraries tab (Figure 3-31).
9. The Vivado Design Suite supports Open IP Example Design flow. To create the example
design using this flow right-click the IP in the Source Window, as shown in Figure 3-32
and select.
X-Ref Target - Figure 3-31
Figure 3-31: Vivado Project – RTL and Constraints Files
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English