Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 437
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Figure 3-46 shows the timing diagram for a typical RLDRAM II configuration 3, burst length
of four with commands being sent to the PHY from a controller. After cal_done is asserted,
the controller begins issuing commands. A single write command is issued by asserting the
cs0 and we0 signals (with ref0 being held Low) and ensuring that addr0 and ba0 are
valid. Because this is a burst length of four configuration, the second command that must
be issued is a No Operation (NOP), that is, all the control signals (cs1, we1, ref1) are held
Low.
Two clock cycles later, the wr_en0/1 signals are asserted, and the wr_data0/1 and
wr_dm0/1 signals are valid for the given write command. In this same clock cycle, a single
read command is issued by asserting cs0 (with we0 and ref0 being held Low) and placing
the associated addresses on addr0 and ba0. Two refresh commands are issued by asserting
cs0/1, ref0/1, and ba0/1. The refresh commands can be issued in the same clock cycle
as long as the memory banking rules are met.
rld_dq Input/Output
Data DQ. This is a bidirectional data port, driven by the FPGA for writes and
by the memory for reads.
rld_qk_p Input
Read Clock QK. This is the read clock returned from the memory edge aligned
with read data on
rld_dq. This clock (in conjunction with QK#) is used by the
PHY to sample the read data on
rld_dq.
rld_qk_n Input
Read Clock QK#. This is the inverted read clock returned from the memory.
This clock (in conjunction with QK) is used by the PHY to sample the read
data on
rld_dq.
rld_reset_n Output
RLDRAM 3 reset pin. This is the active-Low reset to the RLDRAM 3 device (not
used for RLDRAM II).
Table 3-12: Physical Interface Signals (Cont’d)
Signal Direction Description
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