Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 598
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
• Event Delay – The dedicated PHY has internal counters that require this field to specify
the delay values loaded into these counters. The event delay is in units of LPDDR2
SDRAM clock cycles. The MIG IP core does not use these internal counters; therefore,
this field should be all zeros.
• Activate Precharge – The dedicated PHY has internal counters that require this field to
specify the type of LPDDR2 command related to the event delay counter. Valid values
are:
°
00: No action
°
01: Activate
°
10: Precharge
°
11: Precharge/Activate.
The MIG IP core does not use these internal counters; therefore, this field should be all
zeros.
Table 4-23: Auxiliary Output Attributes
Attribute Type Description
MC_AO_WRLVL_EN Vector[3:0]
This attribute specifies whether or not the related Aux_Output is active
during write leveling as specified by the PC_Enable_Calib[1] signal. For
example, this attribute specifies whether ODT is active during write
leveling.
WR_CMD_OFFSET_0 Vector[5:0]
This attribute specifies how long in LPDDR2 SDRAM clock cycles after the
associated write command is executed that the auxiliary output becomes
active. For example, this attribute ensures that the ODT signal is asserted
at the correct clock cycle to meet the JEDEC ODTLon and ODTLoff
specifications.
WR_DURATION_0 Vector[5:0]
This attribute specifies how long in LPDDR2 SDRAM clock cycles the
auxiliary output remains active for a write command. For example, this
attribute ensures that the ODT signal is asserted at the correct clock cycle
to meet the JEDEC ODTLon and ODTLoff specifications.
RD_CMD_OFFSET_0 Vector[5:0]
This attribute specifies how long in LPDDR2 SDRAM clock cycles after the
associated read command is executed that the auxiliary output becomes
active.
RD_DURATION_0 Vector[5:0]
This attribute specifies how long in LPDDR2 SDRAM clock cycles the
auxiliary output remains active for a read command.
WR_CMD_OFFSET_1 Vector[5:0]
This attribute specifies how long in LPDDR2 SDRAM clock cycles after the
associated write command is executed that the auxiliary output becomes
active.
WR_DURATION_1 Vector[5:0]
This attribute specifies how long in LPDDR2 SDRAM clock cycles the
auxiliary output remains active for a write command.
RD_CMD_OFFSET_1 Vector[5:0]
This attribute specifies how long in LPDDR2 SDRAM clock cycles after the
associated read command is executed that the auxiliary output becomes
active.
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V

Summary

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

Introduction

Overview of the DDR3 and DDR2 SDRAM Memory Interface Solution, its architecture, and features.

Features

Highlights enhancements in 7 series FPGA memory interface solutions over earlier families.

Chapter 2: QDR II+ Memory Interface Solution

Introduction

Details the QDR II+ SRAM Memory Interface Solution, its architecture, and usage.

Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions

Introduction

Explains RLDRAM II/III Memory Interface Solutions, covering architecture, usage, and simulation.

Chapter 4: LPDDR2 SDRAM Memory Interface Solution

Introduction

Introduces the LPDDR2 SDRAM Memory Interface Solution, its core components, and features.

Features

Details enhancements in LPDDR2 SDRAM solutions, including performance and hardware blocks.

Chapter 5: Multicontroller Design

Introduction

Describes specifications, supported features, and pinout rules for multicontroller designs.

Chapter 6: Upgrading the ISE/CORE Generator MIG Core in Vivado

Appendix A: General Memory Routing Guidelines