Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
DIGITAL DIE GENERAL-PURPOSE TIMERS
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Interval = (GPTx_LOAD × Prescaler)/Clock Source
(29)
For example, if GPTx_LOAD = 0x100, prescaler = 4, and clock
source = high frequency oscillator, the interval is 39.38 µs (where
high frequency oscillator = 26 MHz).
If the timer is set to count up,
Interval = ((Full Scale − GPTx_LOAD) × Prescaler)/Clock
Source
(30)
Asynchronous Clock Source
Timers are started by setting the enable bit (GPTx_CTL, Bit 4) to
1 in the control register of the corresponding timer. However, when
the timer clock source is the low frequency oscillator, the following
precautions must be taken.
► Do not write to GPTx_CTL if GPTx_STAT, Bit 6 is set.
GPTx_STAT must be read prior to configuring GPTx_CTL. When
GPTx_STAT, Bit 6 is cleared, the register can be modified, ensur-
ing that synchronizing the timer control between the processor
and the timer clock domains is complete. GPTx_STAT, Bit 6 is
the timer busy status bit.
► After clearing the interrupt in GPTx_CLRINT, ensure that the
register write has completed before returning from the interrupt
handler. Use the data synchronization barrier (DSB) instruction if
necessary and check that GPTx_STAT, Bit 7 = 0, as follows:
__asm void asmDSB()
{
nop
DSB
BX LR
}
► The value of a counter can be read at any time by accessing
its value register (GPTx_CURCNT). In an asynchronous configu-
ration, GPTx_CURCNT must always be read twice. If the two
readings are different, this register must be read a third time to
determine the correct value.
GPTx_STAT must be read prior to writing to any timer register
after setting or clearing the enable bit. When GPTx_STAT, Bit 7 is
cleared, registers can be modified, which ensures that the timer has
completed synchronization between the processor and the timer
clock domains. The typical synchronization time is two timer clock
periods.
The GPTx_CTL register enables the counter, selects the mode,
selects the prescale value, and controls the event capture function.
Capture Event Function
The general-purpose timers can capture several interrupt events.
These events are shown in Table 341. Any one of the events
associated with a general-purpose timer can cause a capture of
the 16-bit GPTx_CURCNT register into the 16-bit GPTx_CAPTURE
register. GPTx_CTL has a 5-bit field that can select which event to
capture.
When the selected interrupt event occurs, the GPTx_CURCNT
register is copied into the GPTx_CAPTURE register. When
GPTx_STAT, Bit 1 is set, it indicates that a capture event is
pending. The bit is cleared by writing 1 to GPTx_CLRINT, Bit 1.
The GPTx_CAPTURE register also holds its value and cannot be
overwritten until a 1 is written to GPTx_CLRINT, Bit 1.
Table 341. Capture Event Function
Event Select Range Bits, CON0, Bits[12:8] Timer 0 Capture Source Timer 1 Capture Source Timer 2 Capture Source
0000 WUT UART SYS_WAKE
0001 SYS_WAKE SPI0 Reserved
0010 Reserved Reserved Reserved
0011 Reserved SPI1 Reserved
0100 Reserved I
2
C target DMA error
0101 Reserved I
2
C initiator WUT
0110 DVDD_REG Reserved General-Purpose Timer 0
0111 Reserved Reserved General-Purpose Timer 1
1000 Reserved Reserved Reserved
1001 GPIO Interrupt A Reserved Reserved
1010 GPIO Interrupt B Reserved Reserved
1011 General-Purpose Timer 1 Reserved Reserved
1100 General-Purpose Timer 1 SYS_WAKE Reserved
1101 Flash controller Reserved Reserved
1110 Reserved General-Purpose Timer 0 Reserved
1111 Reserved General-Purpose Timer 2 Reserved

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.