Reference Manual ADuCM356
DIGITAL DIE GENERAL-PURPOSE TIMERS
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Interval = (GPTx_LOAD × Prescaler)/Clock Source
(29)
For example, if GPTx_LOAD = 0x100, prescaler = 4, and clock
source = high frequency oscillator, the interval is 39.38 µs (where
high frequency oscillator = 26 MHz).
If the timer is set to count up,
Interval = ((Full Scale − GPTx_LOAD) × Prescaler)/Clock
Source
(30)
Asynchronous Clock Source
Timers are started by setting the enable bit (GPTx_CTL, Bit 4) to
1 in the control register of the corresponding timer. However, when
the timer clock source is the low frequency oscillator, the following
precautions must be taken.
â–º Do not write to GPTx_CTL if GPTx_STAT, Bit 6 is set.
GPTx_STAT must be read prior to configuring GPTx_CTL. When
GPTx_STAT, Bit 6 is cleared, the register can be modified, ensur-
ing that synchronizing the timer control between the processor
and the timer clock domains is complete. GPTx_STAT, Bit 6 is
the timer busy status bit.
â–º After clearing the interrupt in GPTx_CLRINT, ensure that the
register write has completed before returning from the interrupt
handler. Use the data synchronization barrier (DSB) instruction if
necessary and check that GPTx_STAT, Bit 7 = 0, as follows:
__asm void asmDSB()
{
nop
DSB
BX LR
}
â–º The value of a counter can be read at any time by accessing
its value register (GPTx_CURCNT). In an asynchronous configu-
ration, GPTx_CURCNT must always be read twice. If the two
readings are different, this register must be read a third time to
determine the correct value.
GPTx_STAT must be read prior to writing to any timer register
after setting or clearing the enable bit. When GPTx_STAT, Bit 7 is
cleared, registers can be modified, which ensures that the timer has
completed synchronization between the processor and the timer
clock domains. The typical synchronization time is two timer clock
periods.
The GPTx_CTL register enables the counter, selects the mode,
selects the prescale value, and controls the event capture function.
Capture Event Function
The general-purpose timers can capture several interrupt events.
These events are shown in Table 341. Any one of the events
associated with a general-purpose timer can cause a capture of
the 16-bit GPTx_CURCNT register into the 16-bit GPTx_CAPTURE
register. GPTx_CTL has a 5-bit field that can select which event to
capture.
When the selected interrupt event occurs, the GPTx_CURCNT
register is copied into the GPTx_CAPTURE register. When
GPTx_STAT, Bit 1 is set, it indicates that a capture event is
pending. The bit is cleared by writing 1 to GPTx_CLRINT, Bit 1.
The GPTx_CAPTURE register also holds its value and cannot be
overwritten until a 1 is written to GPTx_CLRINT, Bit 1.
Table 341. Capture Event Function
Event Select Range Bits, CON0, Bits[12:8] Timer 0 Capture Source Timer 1 Capture Source Timer 2 Capture Source
0000 WUT UART SYS_WAKE
0001 SYS_WAKE SPI0 Reserved
0010 Reserved Reserved Reserved
0011 Reserved SPI1 Reserved
0100 Reserved I
2
C target DMA error
0101 Reserved I
2
C initiator WUT
0110 DVDD_REG Reserved General-Purpose Timer 0
0111 Reserved Reserved General-Purpose Timer 1
1000 Reserved Reserved Reserved
1001 GPIO Interrupt A Reserved Reserved
1010 GPIO Interrupt B Reserved Reserved
1011 General-Purpose Timer 1 Reserved Reserved
1100 General-Purpose Timer 1 SYS_WAKE Reserved
1101 Flash controller Reserved Reserved
1110 Reserved General-Purpose Timer 0 Reserved
1111 Reserved General-Purpose Timer 2 Reserved
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