Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 191
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
ODT_MAP
Bank and byte lane
position information for
the ODT. This parameter
is referred to as one of
the Address/Control byte
groups. See
ADDR_MAP
description. This
parameter varies based
on the pinout and should
not be changed manually
in generated design.
See the ADDR_MAP example.
CS_MAP
Bank and byte lane
position information for
the chip select. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
See the ADDR_MAP example.
PARITY_MAP
Bank and byte lane
position information for
the parity bit. Parity bit
exists for RDIMMs only.
See the ADDR_MAP
description. This
parameter varies based on
the pinout and should not
be changed manually in
generated design.
See the ADDR_MAP example.
RAS_MAP
Bank and byte lane
position information for
the RAS command. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
See the ADDR_MAP example.
WE_MAP
Bank and byte lane
position information for
the WE command. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
See the ADDR_MAP example.
Table 1-66: DDR2/DDR3 SDRAM Memory Interface Solution Pinout Parameters (Cont’d)
Parameter Description Example
Send Feedback

Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V