Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 204
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
associated I/Os. In a typical DDR2 configuration, eight of these 10 I/Os are used for the DQs:
one is used for the data mask (DM), and one remains for other signals in the memory
interface.
Xilinx 7 series FPGAs have dedicated clock routing for high-speed synchronization that is
routed vertically within the I/O banks. Thus, DDR2 memory interfaces must be arranged in
the banks vertically and not horizontally. In addition, the maximum height is three banks.
The MIG tool, when available, should be used to generate a pinout for a 7 series DDR2
interface. The MIG tool follows these rules:
• DQS signals for a byte group must be connected to a designated DQS CC pair in the
bank.
• DQ signals and a DM signal must be connected to the byte group pins associated with
the corresponding DQS.
• Control (RAS_N, CAS_N, WE_N, CS_N, CKE, ODT) and address lines must be
connected to byte groups not used for the data byte groups.
• The non-byte groups pins (that is, VRN/VRP pins in HP banks and top/bottom most
pins in HR banks) can be used for an address/control pin, if the following conditions are
met:
°
For HP banks, DCI cascade is used or the bank does not need the VRN/VRP pins, as
in the case of only outputs.
°
The adjacent byte group (T0/T3) is used as an address/control byte group.
°
An unused pin exists in the adjacent byte group (T0/T3) or the CK output is
contained in the adjacent byte group.
• All address/control byte groups must be in the same I/O bank. Address/control byte
groups cannot be split between banks.
• The address/control byte groups must be in the middle I/O bank of interfaces that span
three I/O banks.
• CK must be connected to a p-n pair in one of the control byte groups. Any p-n pair in
the group is acceptable, including SRCC, MRCC, and DQS pins. These pins are
generated for each component and a maximum of four ports/pairs only are allowed
due to I/O pin limitations. Only one CK pair must be connected for one byte group. CK
pairs are generated for each component, and a maximum of four pairs only are allowed
due to I/O pin limitations. This varies based on Memory Clock Selection in the
Memory Options page in the MIG GUI.
• CS_N pins are generated for each component and a maximum of four ports/pairs only
are allowed due to I/O pin limitations.
• For single rank components and DIMMs, only one CKE port is generated.
• For single rank components and DIMMs, the ODT port is repeated based on the number
of components. The maximum number of allowed ports is 3.
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