Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 216
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
1– C_06N 31DQS-N
1– C_05P 30 –
1– C_04N 29 –
1 – C_03 P 28 CCIO-P
1 – C_02 N 27 CCIO-N
1 CKE C_01 P 26 CCIO-P
1 ODT C_00 N 25 CCIO-N
1 RAS_N B_11 P 24 CCIO-P
1 CAS_N B_10 N 23 CCIO-N
1 WE_N B_09 P 22 CCIO-P
1BA2 B_08 N 21 CCIO-N
1CK_P B_07 P 20 DQS-P
1CK_N B_06 N 19 DQS-N
1BA1 B_05 P 18 –
1BA0 B_04 N 17 –
1CS_N B_03 P 16 –
1 A14 B_02 N 15 –
1 A13 B_01 P 14 –
1 A12 B_00 N 13 –
1 A11 A_11 P 12 –
1 A10 A_10 N 11 –
1A9 A_09 P 10 –
1A8 A_08 N 9 –
1A7 A_07 P 8 DQS-P
1A6 A_06 N 7 DQS-N
1A5 A_05 P 6 –
1A4 A_04 N 5 –
1A3 A_03 P 4 –
1A2 A_02 N 3 –
1A1 A_01 P 2 –
1A0 A_00 N 1 –
1VRN – SE 0 –
2VRP – SE 49 –
2DQ31 D_11 P 48 –
Table 1-70: 32-Bit DDR3 Interface Contained in Two Banks (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V