Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 233
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
• Check the reset to ensure the polarity is correct and the signal is clean. The reset signal
must be applied for a minimum pulse width of 5 ns.
• Check terminations by using this user guide as a guideline.
• Perform general signal integrity analysis.
°
IBIS simulations should run to ensure terminations, ODT, and output drive strength
settings are appropriate.
°
Observe DQ/DQS on a scope at the memory. View the alignment of the signals and
analyze the signal integrity during both writes and reads.
°
Observe the Address and Command signals on a scope at the memory. View the
alignment and analyze the signal integrity.
• Verify the memory parts on the board(s) in test are the correct part(s) set through the
MIG tool. The timing parameters and signals widths (that is, address, bank address)
must match between the RTL and physical parts. Read/write failures can occur due to a
mismatch.
• Verify SDRAM pins are behaving correctly. Look for floating or grounded signals. It is
rare, but manufacturing issues with the memory devices can occur and result in
calibration failures.
• If Data Mask (DM) is not being used, ensure DM is tied Low at the memory with the
appropriate termination as noted in the memory data sheet.
• Measure the CK/CK_n, DQS/DQS_n, and system clocks for duty cycle distortion and
general signal integrity.
•If internal V
REF
is used, ensure the constraints are set appropriately according to the
Xilinx Constraints Guide. When the constraints are applied properly, a note similar to
the following appears in the .bgn BitGen report file:
°
There were two CONFIG constraint(s) processed from example_top.pcf.
CONFIG INTERNAL_VREF_BANK12 = 0.75
CONFIG INTERNAL_VREF_BANK14 = 0.75
•Check the iodelay_ctrl ready signal.
• Check the PLL lock.
•Check the phaser_ref lock signal.
•Bring the init_calib_complete out to a pin and check with a scope.
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