Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 237
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
dbg_rddata_r
Read data read out of the IN_FIFO for the DQS group selected through
dbg_dqs on the VIO. This is a 64-bit bus. This debug port does not
capture ECC data.
dbg_fine_adjust_done_r Asserts after fine adjustment is completed in DQS found calibration.
dbg_cmd_wdt_err_w
Watch dog timeout error from Traffic Generator when the user
interface is not processing the command from traffic generator.
dbg_rd_wdt_err_w
Watch dog timeout error from Traffic Generator when no read data is
available from the user interface.
dbg_wr_wdt_err_w
Watch dog timeout error from Traffic Generator when no write data is
taken by the user interface.
dbg_tg_compare_error
Sticky bit from the internal Traffic Generator asserted when a data error
is found after calibration is completed.
dbg_cmp_data_valid
Valid signal showing that the compare data from Traffic Generator is
valid.
dbg_cmp_error
Asserts when compare data is not matching the read data from User
Interface.
dbg_cmp_data_r Register version of compare data from the Traffic Generator.
dbg_dq_error_bytelane_cmp
Indicates which byte has data comparison error for the Traffic
Generator.
dbg_cumlative_dq_lane_error
Indicates which byte has data comparison error for the Traffic
Generator. This is a sticky status signal and stays asserted until cleared
manually using the dbg_clear_error.
dbg_cmp_addr_i The start address of the burst for which the first data error occurred.
dbg_cmp_bl_i Burst length of the burst for which the first data error occurred.
dbg_mcb_cmd_full_i
Memory Controller command FIFO full status when the first data error
occurred
dbg_mcb_wr_full_i
Memory Controller write data FIFO full status when the first data error
occurred.
dbg_mcb_rd_empty_i
Memory Controller read data FIFO empty status when the first data
error occurred.
dbg_ddrx_ila_rdpath_765_764[0] Signifies PRBS Read Level Stage Start
dbg_ddrx_ila_rdpath_765_764[1] Signifies PRBS Read Level Stage Done
dbg_wl_state_r
State variable for the Write Leveling State Machine. States can be
decoded in the ddr_phy_wrlvl.v module.
dbg_dqs_cnt_r
Signifies the DQS byte group being calibrated during Write Leveling.
The algorithm sequentially steps through the DQS byte groups until
Write Leveling completes successfully or a data byte group fails due a
0 to 1 transition not being detected on DQ.
dbg_wl_edge_detect_valid_r Signifies valid time Write Leveling algorithm is searching for edge.
dbg_rd_data_edge_detect_r_by_dqs Signifies Write Leveling calibration found the 0 to 1 edge transition.
Table 1-74: DDR2/DDR3 Debug Signals (Cont’d)
Signal Name Description
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