Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 242
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
vio_instr_mode_value See Table 1-83.
vio_bl_mode_value See Table 1-83.
vio_fixed_bl_value See Table 1-83.
vio_data_mask_gen Enables Traffic Generator Data Mask Generation
vio_pause_traffic See Table 1-83.
vio_fixed_instr_value See Table 1-83.
dbg_clear_error See Table 1-83.
vio_tg_rst Currently Unused
wdt_en_w Enable Watch Dog Timer in Traffic Generator
win_start See Table 1-85.
win_sel_pi_pon See Table 1-85.
vio_dbg_sel_pi_incdec See Table 1-85.
vio_dbg_sel_po_incdec See Table 1-85.
vio_dbg_pi_f_inc See Table 1-85.
vio_dbg_pi_f_dec See Table 1-85.
vio_dbg_po_f_inc See Table 1-85.
vio_dbg_po_f_dec See Table 1-85.
vio_dbg_po_f_stg23_sel See Table 1-85.
vio_win_byte_select_inc See Table 1-85.
vio_win_byte_select_dec See Table 1-85.
vio_sel_mux_rdd[3:0] See Table 1-85.
vio_tg_simple_data_sel Currently Unused
VIO Signals (Status)
win_start Status signal reflecting the logic level of win_start input.
dbg_pi_counter_read_val See Table 1-85.
pi_win_left_ram_out See Table 1-85.
pi_win_right_ram_out See Table 1-85.
win_active See Table 1-85.
dbg_win_chk
Debug signals from window margin check module. See _chk_win.v file
for details.
win_current_bit Unused for DDR3 Interface
win_current_byte[3:0] See Table 1-85.
win_byte_select See Table 1-85.
po_win_left_ram_out See Table 1-85.
po_win_right_ram_out See Table 1-85.
Table 1-74: DDR2/DDR3 Debug Signals (Cont’d)
Signal Name Description
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English