Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 267
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
b. Observe the dbg_rddata_r and cmp_data_r signals in Vivado logic analyzer
feature.
- Are errors seen on a data bit/s belonging to a certain DQS group(s)?
- Does the data appear shifted, garbage, swapped, and others?
• Determine if errors are seen on accesses to a certain address, bank, or rank of the
memory.
a. Set the ILA trigger to cmp_error = 1.
b. Set the VIO cores.
vio_modify_enable = 1
vio_data_mode_value = 2
vio_addr_mode_value = 3
c. Observe the cmp_addr_i bits of the error_status[31:0] in Vivado logic
analyzer.
• Determine if errors only occur for certain data patterns or sequences. This can indicate
a shorted or open connection on the PCB or can also indicate an SSO or crosstalk issue.
a. Set the LA trigger to cmp_error = 1.
b. Set the VIO cores.
vio_modify_enable = 1
vio_instr_mode_value = 2
vio_data_mode_value = 2
vio_addr_mode_value = 3
c. Observe the dbg_rddata_r and cmp_data_r signals and the cmp_addr_i bits of
the error_status[31:0] bus in the Vivado logic analyzer feature.
d. Repeat steps 1 to 3 with setting vio_data_mode_value to values varying from
3-F.
• Determine the frequency and reproducibility of the error.
°
Does the error occur after every calibration or reset?
°
Does the error occur at specific temperature or voltage conditions?
• Determine if the error is correctable.
°
Rewriting, rereading, resetting, and recalibrating.
Note:
vio_pause_traffic should be asserted and deasserted each time the VIO inputs are
changed.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English