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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
30
5
UG586 Novemb
er 30, 2016
www
.xilinx.com
Chapter 2:
QDR II+ Memory Interface Solution
7.
Clicking the
Generate Output Products
option brings up the
Manage Outputs
windo
w
(
Figure
2-33
).
X-Ref Targ
et - Figure 2-32
Figure 2-32:
Genera
te R
TL and Constr
aints
X-Ref Targ
et - Figure 2-33
Figure 2-33:
Genera
te Window
S
e
n
d
F
e
e
d
b
a
c
k
304
306
Table of Contents
Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.1
1
Table of Contents
18
Ch. 1: DDR3 and DDR2 SDRAM Memory Interface Solution
20
Introduction
20
Features
20
Using MIG in the Vivado Design Suite
21
Customizing and Generating the Core
29
MIG Output Options
29
Pin Compatible FPGAs
30
Creating 7 Series FPGA DDR3 Memory Controller Block Design
32
Memory Selection
32
Controller Options
33
Create Custom Part
35
AXI Parameter Options
37
Setting DDR3 Memory Parameter Option
39
FPGA Options
40
Bank Selection
44
Summary
46
Memory Model License
47
PCB Information
48
Design Notes
48
Vivado Integrated Design Flow for MIG
49
Directory Structure and File Descriptions
57
Output Directory Structure
57
Directory and File Contents
58
<component name>/example_design/
58
example_design/rtl
58
example_design/rtl/traffic_gen
59
<component name>/example_design/par
59
<component name>/example_design/sim
60
<component name>/user_design
60
user_design/rtl/clocking
61
user_design/rtl/controller
61
user_design/rtl/ip_top
62
user_design/rtl/phy
62
user_design/rtl/ui
63
<component name>/user_design/xdc
63
Verify Pin Changes and Update Design
64
Quick Start Example Design
65
Overview
65
Implementing the Example Design
66
Simulating the Example Design (for Designs with the Standard User Interface)
66
Traffic Generator Operation
67
Modifying the Example Design
68
Modifying Port Address Space
72
Traffic Generator Signal Description
73
Memory Initialization and Traffic Test Flow
76
Memory Initialization
76
Traffic Test Flow
76
Simulating the Example Design (for Designs with the AXI4 Interface)
77
Setting Up for Simulation
82
Simulation Flow Using IES and VCS Script Files
82
Simulation Flow Using Vivado Simulator
83
Simulation Flow Using Questa Advanced Simulator
84
Simulation Flow Using VCS
85
Simulation Flow Using IES
87
Synplify Pro Black Box Testing
89
Core Architecture
90
Overview
90
User FPGA Logic
91
AXI4 Slave Interface Block
91
User Interface Block and User Interface
91
Memory Controller and Native Interface
91
PHY and the Physical Interface
91
IDELAYCTRL
91
User Interface
92
app_addr[ADDR_WIDTH – 1:0]
93
app_cmd[2:0]
93
app_en
94
app_hi_pri
94
app_wdf_data[APP_DATA_WIDTH – 1:0]
94
app_wdf_end
94
app_wdf_mask[APP_MASK_WIDTH – 1:0]
94
app_wdf_wren
94
app_rdy
94
app_rd_data[APP_DATA_WIDTH – 1:0]
95
app_rd_data_end
95
app_rd_data_valid
95
app_wdf_rdy
95
app_ref_req
95
app_ref_ack
95
app_zq_req
95
app_zq_ack
95
ui_clk_sync_rst
96
ui_clk
96
init_calib_complete
96
AXI4 Slave Interface Block
96
AXI4 Slave Interface Parameters
97
AXI4 Slave Interface Signals
98
Arbitration in AXI Shim
100
Time Division Multiplexing (TDM)
100
Round-Robin
100
Read Priority (RD_PRI_REG)
100
Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT)
100
Write Priority (WRITE_PRIORITY, WRITE_PRIORITY_REG)
101
AXI4-Lite Slave Control/Status Register Interface Block
101
ECC Enable/Disable
101
Single Error and Double Error Reporting
101
Interrupt Generation
102
Fault Collection
102
Fault Injection
102
AXI4-Lite Slave Control/Status Register Interface Parameters
102
AXI4-Lite Slave Control/Status Register Interface Signals
103
AXI4-Lite Slave Control/Status Register Map
104
AXI4-Lite Slave Control/Status Register Map Detailed Descriptions
105
ECC_STATUS
105
ECC_EN_IRQ
105
ECC_ON_OFF
106
CE_CNT
106
CE_FFA[31:0]
107
CE_FFA[63:32]
107
CE_FFD[31:0]
107
CE_FFD[63:32]
107
CE_FFD[95:64]
108
CE_FFD[127:96]
108
CE_FFE
108
UE_FFA[31:0]
109
UE_FFA[63:32]
109
UE_FFD[31:0]
110
UE_FFD[63:32]
110
UE_FFD[95:64]
110
UE_FFD[127:96]
111
UE_FFE
111
FI_D0
111
FI_D1
112
FI_D2
112
FI_D3
113
FI_ECC
113
User Interface Block
114
Native Interface
114
Command Request Signals
114
accept
115
use_addr
115
data_buf_addr
115
Write Command Signals
116
wr_data
116
wr_data_addr
116
wr_data_mask
116
wr_data_en
116
wr_data_offset
117
Read Command Signals
117
rd_data
117
rd_data_addr
117
rd_data_en
117
rd_data_offset
117
Native Interface Maintenance Command Signals
118
app_ref_req
118
app_ref_ack
118
app_zq_req
118
app_zq_ack
118
Clocking Architecture
119
Internal (FPGA) Logic Clock
120
Write Path (Output) I/O Logic Clock
121
Read Path (Input) I/O Logic Clock
121
IDELAY Reference Clock
121
Memory Controller
122
Bank Machines
123
Rank Machines
124
Column Machine
124
Arbitration Block
124
Reordering
124
Precharge Policy
126
Error Correcting Code
126
Read-Modify-Write
128
ECC Self-Test Functionality
130
PHY
131
Overall PHY Architecture
131
Memory Initialization and Calibration Sequence
134
I/O Architecture
135
PHY Control Block
135
Command Path
140
Datapath
142
Power-Saving Features
144
Calibration and Initialization Stages
144
Memory Initialization
144
PHASER_IN Phase Lock
145
PHASER_IN DQSFOUND Calibration
145
Write Leveling
146
Multi-Purpose Register Read Leveling
149
OCLKDELAYED Calibration
150
Write Calibration
152
Read Leveling
154
PRBS Read Leveling
157
Dynamic Calibration and Periodic Read Behavior
157
Temperature Monitor
158
Memory Controller to PHY Interface
159
Designing with the Core
162
Interfacing to the Core
163
AXI4 Slave Interface
163
AXI Addressing
163
Upsizing
164
User Interface
164
Command Path
166
Write Path
168
Read Path
170
User Refresh
170
User ZQ
171
Native Interface
172
User Refresh
174
User ZQ
174
Physical Layer Interface (Non-Memory Controller Design)
174
Customizing the Core
180
Design Guidelines
192
DDR3 SDRAM
192
Design Rules
192
Bank and Pin Selection Guides for DDR3 Designs
193
Pin Swapping
194
Bank Sharing Among Controllers
194
System Clock, PLL and MMCM Locations, and Constraints
194
DDR3 Component PCB Routing
195
VREF
195
VCCAUX_IO
195
Power System and Plane Discontinuities
196
Termination
196
Trace Lengths
198
Configuration
201
I/O Standards
203
DDR2 SDRAM
203
Design Rules
203
Pin Assignments
203
Bank and Pin Selection Guides for DDR2 Designs
203
Bank Sharing Among Controllers
205
Pin Swapping
205
Internal VREF
205
System Clock, PLL Location, and Constraints
206
Configuration
206
Termination
208
I/O Standards
209
Trace Lengths
209
Clocking
210
Input Clock Guidelines
210
Sharing sys_clk between Controllers
212
Information on Sharing BUFG Clock (phy_clk)
213
Information on Sync_Pulse
213
DDR3 Pinout Examples
213
Debugging DDR3/DDR2 Designs
228
Finding Help on Xilinx.com
228
Documentation
228
Solution Centers
228
Answer Records
228
Technical Support
229
Debug Tools
229
Example Design
229
Debug Signals
230
Vivado Design Suite Debug Feature
230
Reference Boards
231
Hardware Debug
231
General Checks
232
Calibration Stages
234
Memory Initialization
234
Determine the Failing Calibration Stage
235
Debug Signals
236
Debugging PHASER_IN PHASELOCKED Calibration Failures (dbg_pi_phaselock_err = 1)
243
Calibration Overview
243
Debug
243
Debugging PHASER_IN DQSFOUND Calibration Failures (dbg_pi_dqsfound_err = 1)
243
Calibration Overview
243
Debug
244
Expected Vivado Logic Analyzer Tool Results
246
Debugging Write Leveling Failures (dbg_wrlvl_err = 1)
246
Calibration Overview
246
Debug
247
Expected Vivado Logic Analyzer Tool Results
248
Debugging MPR Read Leveling Failures – DDR3 Only (dbg_rdlvl_err[1] = 1)
249
Calibration Overview
249
Debug
250
Expected Vivado Logic Analyzer Tool Results
251
Debugging OCLKDELAYED Calibration Failures
252
Calibration Overview
252
Debug
252
Debugging Write Calibration Failures (dbg_wrcal_err = 1)
253
Calibration Overview
253
Debug
254
Expected Vivado Logic Analyzer Tool Results
257
Debugging Read Leveling Failures (dbg_rdlvl_err[0] = 1)
258
Calibration Overview
258
Debug
258
Expected Vivado Logic Analyzer Tool Results
260
Debugging PRBS Read Leveling Failures
261
Calibration Overview
261
Debug
261
Calibration Times
263
Debugging Data Errors
263
General Checks
263
Replicating the Error Using the Traffic Generator
263
Isolating the Data Error
266
Determining If a Data Error is Due to the Write or Read
268
Checking and Varying Read Timing
270
Automated Window Check
270
Manual Window Check
271
Analyzing Calibration Results
271
Interface Debug
272
AXI4-Lite Interfaces
272
AXI4-Stream Interfaces
272
CLOCK_DEDICATED_ROUTE Constraints
273
System Clock
273
Reference Clock
273
Ch. 2: QDR II+ Memory Interface Solution
274
Introduction
274
Using MIG in the Vivado Design Suite
275
Customizing and Generating the Core
285
MIG Output Options
285
Pin Compatible FPGAs
286
Creating the 7 Series FPGA QDR II+ SRAM Design
287
Memory Selection
287
Controller Options
289
Create Custom Part
290
Memory Options
291
FPGA Options
292
Extended FPGA Options
294
I/O Planning Options
295
Bank Selection
296
System Pins Selection
298
Summary
299
PCB Information
300
Design Notes
300
Finish
300
Vivado Integrated Design Flow for MIG
301
Directory Structure and File Descriptions
309
Output Directory Structure
309
Directory and File Contents
310
<component name>/example_design/
310
<component name>/user_design
312
user_design/rtl/clocking
312
user_design/rtl/phy
313
<component name>/user_design/xdc
314
Verify Pin Changes and Update Design
314
Core Architecture
317
Overview
317
User Interface
319
Command Request Signals
319
Interfacing with the Core through the Client Interface
321
Clocking Architecture
322
Physical Interface
324
Interfacing with the Memory Device
325
PHY Architecture
325
Write Path
327
Output Architecture
327
Output Path
329
PHY Control Block
330
Pre-FIFO
331
Read Path
332
Data Capture
332
Calibration
333
Calibration of Read Clock and Data
334
Implementation Details
334
Data Alignment and Valid Generation
335
Write Calibration
336
Customizing the Core
337
Design Guidelines
342
Design Rules
342
Bank Sharing Among Controllers
343
Trace Length Requirements
343
Pinout Requirements
344
System Clock, PLL Location, and Constraints
345
Configuration
345
Termination
347
I/O Standards
347
Clocking
348
Input Clock Guidelines
348
Sharing sys_clk between Controllers
350
Information on Sharing BUFG Clock (phy_clk)
351
Information on Sync_Pulse
351
Debugging QDR II+ SRAM Designs
351
Introduction
351
Debug Tools
352
Example Design
352
Debug Signals
353
Vivado Design Suite Debug Feature
353
Simulation Debug
353
Verifying the Simulation Using the Example Design
354
Simulation Flow Using IES and VCS Script Files
354
Simulation Flow Using Vivado Simulator
354
Simulation Flow Using Questa Advanced Simulator
356
Simulation Flow Using VCS
357
Simulation Flow Using IES
359
Memory Initialization
361
Calibration
362
Test Bench
363
Proper Write and Read Commands
364
Synthesis and Implementation Debug
365
Verify Successful Synthesis and Implementation
365
Verify Modifications to the MIG Tool Output
365
Identifying and Analyzing Timing Failures
365
Hardware Debug
366
Clocking
366
Verify Board Pinout
367
Run Signal Integrity Simulation with IBIS Models
367
Run the Example Design
367
Debugging Common Hardware Issues
367
Isolating Bit Errors
368
Debugging the Core
368
Margin Check
370
Automated Margin Check
371
DEBUG_PORT Signals
372
Write Init Debug Signals
374
Read Stage 1 Calibration Debug Signals
375
Read Stage 2 Calibration Debug
376
CLOCK_DEDICATED_ROUTE Constraints
378
System Clock
378
Reference Clock
378
Ch. 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
379
Introduction
379
Using MIG in the Vivado Design Suite
380
Customizing and Generating the Core
388
MIG Output Options
388
Pin Compatible FPGAs
389
Creating the 7 Series FPGAs RLDRAM II/RLDRAM 3 Memory Design
390
Memory Selection
390
Controller Options
392
Memory Options
393
FPGA Options
395
Extended FPGA Options
397
Bank Selection
397
System Pins Selection
399
Summary
400
PCB Information
401
Design Notes
401
Finish
402
Vivado Integrated Design Flow for MIG
402
Directory Structure and File Descriptions
410
Output Directory Structure
410
Directory and File Contents
411
<component name>/example_design/
411
<component name>/user_design/
413
user_design/rtl/controller
413
user_design/rtl/ui
414
user_design/rtl/phy
414
user_design/rtl/xdc
415
Verify Pin Changes and Update Design
415
Quick Start Example Design
417
Overview
417
Implementing the Example Design
417
Simulating the Example Design (for Designs with the Standard User Interface)
417
Traffic Generator Operation
419
Modifying the Example Design
420
Core Architecture
424
Overview
424
Client Interface
427
Command Request Signals
427
Interfacing with the Core through the Client Interface
429
Clocking Architecture
434
Physical Interface
436
Memory Controller
439
PHY Architecture
440
Write Path
443
Output Architecture
443
Read Path
446
Data Capture
446
Calibration
447
Calibration of Read Clock and Data
448
Implementation Details
448
Data Alignment and Valid Generation
451
Write Calibration
452
Customizing the Core
458
Design Guidelines
466
Design Rules
466
Bank Sharing Among Controllers
466
Trace Length Requirements
466
Pinout Requirements
467
RLDRAM II
468
RLDRAM 3
469
System Clock, PLL Location, and Constraints
470
Configuration
471
Termination
472
Manual Pinout Changes
473
I/O Standards
476
Clocking
478
Input Clock Guidelines
478
Sharing sys_clk between Controllers
480
Information on Sharing BUFG Clock (phy_clk)
481
Information on Sync_Pulse
481
Debugging RLDRAM II and RLDRAM 3 Designs
481
Introduction
481
Debug Tools
482
Example Design
482
Debug Signals
482
Vivado Design Suite Debug Feature
483
Simulation Debug
483
Verifying the Simulation Using the Example Design
483
Simulation Flow Using IES and VCS Script Files
484
Simulation Flow Using Vivado Simulator
484
Simulation Flow Using Questa Advanced Simulator
486
Simulation Flow Using VCS
487
Simulation Flow Using IES
489
Memory Initialization
492
Calibration
492
Test Bench
495
Proper Write and Read Commands
495
Synthesis and Implementation Debug
497
Verify Successful Synthesis and Implementation
497
Verify Modifications to the MIG Tool Output
497
Identifying and Analyzing Timing Failures
497
Hardware Debug
498
Clocking
498
Verify Board Pinout
499
Run Signal Integrity Simulation with IBIS Models
499
Run the Example Design
499
Debugging Common Hardware Issues
499
Isolating Bit Errors
500
Debugging the Core
501
DEBUG_PORT Signals
502
Write Init Debug Signals
505
Read Stage 1 Calibration Debug Signals
506
Read Stage 2 Calibration Debug
507
Write Calibration Debug Map
509
Margin Check
510
Automated Margin Check
511
Debugging Write Calibration
513
CLOCK_DEDICATED_ROUTE Constraints
514
System Clock
514
Reference Clock
515
Ch. 4: LPDDR2 SDRAM Memory Interface Solution
516
Introduction
516
Features
516
Using MIG in the Vivado Design Suite
517
Customizing and Generating the Core
525
MIG Output Options
525
Pin Compatible FPGAs
527
Creating 7 Series FPGA LPDDR2 SDRAM Memory Controller Block Design
528
Memory Selection
528
Controller Options
528
Create Custom Part
530
Setting LPDDR2 SDRAM Memory Parameter Option
531
FPGA Options
532
Bank Selection
534
Summary
537
Memory Model License
538
PCB Information
539
Design Notes
539
Vivado Integrated Design Flow for MIG
540
Directory Structure and File Descriptions
547
Output Directory Structure
547
Directory and File Contents
548
<component name>/example_design/
548
example_design/rtl
548
example_design/rtl/traffic_gen
549
<component name>/example_design/par
549
<component name>/example_design/sim
550
<component name>/user_design
550
user_design/rtl/clocking
551
user_design/rtl/controller
551
user_design/rtl/ip_top
552
user_design/rtl/phy
552
user_design/rtl/ui
553
<component name>/user_design/xdc
553
Verify Pin Changes and Update Design
554
Quick Start Example Design
555
Overview
555
Simulating the Example Design (for Designs with the Standard User Interface)
556
Traffic Generator Operation
557
Modifying the Example Design
558
Modifying Port Address Space
562
Traffic Generator Signal Description
563
Memory Initialization and Traffic Test Flow
566
Memory Initialization
566
Traffic Test Flow
566
Setting Up for Simulation
567
Simulation Flow Using IES and VCS Script Files
568
Simulation Flow Using Vivado Simulator
569
Simulation Flow Using Questa Advanced Simulator
570
Simulation Flow Using VCS
571
Simulation Flow Using IES
573
Core Architecture
575
Overview
575
User FPGA Logic
575
User Interface Block and User Interface
576
Memory Controller and Native Interface
576
PHY and the Physical Interface
576
IDELAYCTRL
576
User Interface
577
app_addr[ADDR_WIDTH – 1:0]
578
app_cmd[2:0]
578
app_en
578
app_hi_pri
578
app_wdf_data[APP_DATA_WIDTH – 1:0]
578
app_wdf_end
578
app_wdf_mask[APP_MASK_WIDTH – 1:0]
579
app_wdf_wren
579
app_rdy
579
app_rd_data[APP_DATA_WIDTH – 1:0]
579
app_rd_data_end
579
app_rd_data_valid
579
app_wdf_rdy
579
app_ref_req
580
app_ref_ack
580
app_zq_req
580
app_zq_ack
580
ui_clk_sync_rst
580
ui_clk
580
init_calib_complete
580
User Interface Block
581
Native Interface
581
Command Request Signals
581
accept
582
use_addr
582
data_buf_addr
582
Write Command Signals
582
wr_data
583
wr_data_addr
583
wr_data_mask
583
wr_data_en
583
wr_data_offset
583
Read Command Signals
583
rd_data
584
rd_data_addr
584
rd_data_en
584
rd_data_offset
584
Native Interface Maintenance Command Signals
584
app_ref_req
585
app_ref_ack
585
app_zq_req
585
app_zq_ack
585
Clocking Architecture
585
Internal (FPGA) Logic Clock
587
Write Path (Output) I/O Logic Clock
587
Read Path (Input) I/O Logic Clock
587
IDELAY Reference Clock
587
Memory Controller
588
Bank Machines
589
Rank Machines
590
Column Machine
590
Arbitration Block
590
Reordering
590
Precharge Policy
592
PHY
592
Overall PHY Architecture
592
Memory Initialization and Calibration Sequence
594
I/O Architecture
595
PHY Control Block
596
Command Path
600
Datapath
602
Calibration and Initialization Stages
604
Memory Initialization
604
Read Leveling
604
Read Valid Calibration
607
PRBS Read Leveling
607
Phase Detector
608
Memory Controller to PHY Interface
609
Designing with the Core
611
Interfacing to the Core
611
User Interface
612
Command Path
614
Write Path
616
Read Path
617
User ZQ
618
Native Interface
619
User ZQ
621
Customizing the Core
621
Design Guidelines
631
LPDDR2 SDRAM
631
Design Rules
631
Pin Assignments
631
Bank and Pin Selection Guides for LPDDR2 Designs
631
Bank Sharing Among Controllers
633
Pin Swapping
633
Internal VREF
633
System Clock, MMCM Location, and Constraints
633
Configuration
634
Termination
635
I/O Standards
636
Trace Lengths
636
Clocking
637
Input Clock Guidelines
637
Sharing sys_clk between Controllers
639
Information on Sharing BUFG Clock (phy_clk)
640
Information on Sync_Pulse
640
LPDDR2 Pinout Examples
640
CLOCK_DEDICATED_ROUTE Constraints
642
System Clock
642
Reference Clock
642
Ch. 5: Multicontroller Design
644
Introduction
644
Using MIG in the Vivado Design Suite
645
Customizing and Generating the Core
653
Multiple Controllers
653
Creating 7 Series FPGA Multicontroller Block Design
655
Memory Selection
655
FPGA Options
656
Extended FPGA Options Page
657
System Clock Pins Selection
658
System Clock Sharing
658
Vivado Integrated Design Flow for MIG
659
Directory Structure
667
Ch. 6: Upgrading the ISE/CORE Generator MIG Core in Vivado
668
Appx. A: General Memory Routing Guidelines
669
Appx. B: Additional Resources and Legal Notices
677
Xilinx Resources
677
References
677
Please Read: Important Legal Notices
678
Other manuals for Xilinx Zynq-7000
Design Guide
77 pages
Getting Started Guide
50 pages
Application Note
14 pages
Manual
8 pages
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Xilinx Zynq-7000 Specifications
General
Brand
Xilinx
Model
Zynq-7000
Category
Motherboard
Language
English
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