Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 305
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
7. Clicking the Generate Output Products option brings up the Manage Outputs window
(Figure 2-33).
X-Ref Target - Figure 2-32
Figure 2-32: Generate RTL and Constraints
X-Ref Target - Figure 2-33
Figure 2-33: Generate Window
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