Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 398
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
For customized settings, click Deselect Banks and select the appropriate bank and memory
signals. Click Next to move to the next page if the default setting is used. To unselect the
banks that are selected, click Deselect Banks. To restore the defaults, click Restore
Defaults. VCCAUX_IO groups are shown for HP banks in devices with these groups using
dashed lines. VCCAUX_IO is common to all banks in these groups. The memory interface
must have the same VCCAUX_IO for all banks used in the interface. MIG automatically sets
the VCCAUX_IO constraint appropriately for the data rate requested.
For devices implemented with SSI technology, the SLRs are indicated by a number in the
header in each bank, for example, SLR 1. Interfaces cannot span across Super Logic Regions.
Not all devices have Super Logic Regions.
X-Ref Target - Figure 3-22
Figure 3-22: Bank Selection Page
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V