Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 464
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
DK_MAP
Bank and byte lane position
information for the DK/DK#. 8-bit
parameter provided per pair of
signals.
• [3:0] – Byte lane position within a
bank. Values of 0, 1, 2, or 3 are
supported.
• [7:4] – Bank position. Values of 0, 1,
or 2 are supported
This parameter varies based on the
pinout and should not be changed
manually in generated design.
Upper-most Data or Address/Control byte group
selected bank is referred to as Bank 0 in
parameters notation. Numbering of banks is 0, 1,
and 2 from top to bottom.
Byte groups T0, T1, T2, and T3 are numbered in
parameters as 3, 2, 1, and 0, respectively.
96'h00_00_00_00_00_00_00_00_00_00_10_13 =
This parameter is denoted for 12 clock pairs with
8 bits for each clock pin. In this case, two clock
pairs are used. Ordering of parameters is from
MSB to LSB (that is, DK[0]/ DK#[0] corresponds to
the 8 LSBs of the parameter).
8'h13 = DK/DK# placed in bank 1, byte lane 3.
8'h20 = DK/DK# placed in bank 2, byte lane 0.
QK_MAP
Bank and byte lane position
information for the QK/QK#. 8-bit
parameter provided per pair of
signals.
• [3:0] – Byte lane position within a
bank. Values of 0, 1, 2, or 3 are
supported.
• [7:4] – Bank position. Values of 0, 1,
or 2 are supported
This parameter varies based on the
pinout and should not be changed
manually in generated design.
See the DK_MAP example for parameter values
notation.
8'h11 = QK/QK# placed in bank 1, byte lane 1.
8'h22 = QK/QK# placed in bank 2, byte lane 2.
CS_MAP
Bank and byte lane position
information for the chip select. 12-bit
parameter provided per pin.
• [3:0] – Bit position within a byte
lane. Values of [0, 1, 2, . . ., A, B] are
supported.
• [7:4] – Byte lane position within a
bank. Values of 0, 1, 2, or 3 are
supported.
• [11:8] – Bank position. Values of 0,
1, or 2 are supported
This parameter varies based on the
pinout and should not be changed
manually in generated design.
See the CK_MAP example.
WE_MAP
Bank and byte lane position
information for the write enable. See
CS_MAP description. This parameter
varies based on the pinout and
should not be changed manually in
generated design.
See the CK_MAP example.
Table 3-15: RLDRAM II Memory Interface Solution Pinout Parameters (Cont’d)
Parameter Description Example
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English