Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 465
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
REF_MAP
Bank and byte lane position
information for the refresh signal.
See CS_MAP description. This
parameter varies based on the pinout
and should not be changed manually
in generated design.
See the CK_MAP example.
ADDR_MAP
Bank and byte lane position
information for the address. See
CS_MAP description. This parameter
varies based on the pinout and
should not be changed manually in
generated design.
See the CK_MAP example.
BANK_MAP
Bank and byte lane position
information for the bank address. See
CS_MAP description. This parameter
varies based on the pinout and
should not be changed manually in
generated design.
See the CK_MAP example.
DQTS_MAP
Bank and byte lane position
information for the 3-state control.
See CS_MAP description. This
parameter varies based on the pinout
and should not be changed manually
in generated design.
See the CK_MAP example.
DM_MAP
Bank and byte lane position
information for the data mask. See
CS_MAP description. This parameter
varies based on the pinout and
should not be changed manually in
generated design.
See the CK_MAP example.
DATA0_MAP,
DATA1_MAP,
DATA2_MAP,
DATA3_MAP,
DATA4_MAP,
DATA5_MAP,
DATA6_MAP,
DATA7_MAP
Bank and byte lane position
information for the data bus. See
CS_MAP description. This parameter
varies based on the pinout and
should not be changed manually in
generated design.
See the CK_MAP example.
Table 3-15: RLDRAM II Memory Interface Solution Pinout Parameters (Cont’d)
Parameter Description Example
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English