Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 474
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Table 3-18 shows the byte lane with the Data Mask (DM) placed on the 3-state location.
While the DM can share the OSERDES location with the 3-state control, they cannot share
the same location in the OUT_FIFO in the PHY. Thus some signals from the OUT_FIFO have
to shift as shown in Table 3-18. In this case, the direction of the shift is determined on the
byte lane location, with byte lanes 0, 1 shifted up, and 2, 3 shifted down. In this case, the
PHY merges the 3-state control with the DM to share the same OSERDES location.
The byte lane parameters for Table 3-18 are shown in Table 3-19.
Table 3-18: Example RLDRAM II Byte Lane #3, Shared 3-State with DM in Byte Lane #1
Bank
Byte
Lane
Bit MAP DDR
Byte
Group
I/O
Type
I/O
Number
Special
Designation
BITLANES
XDC
01
9 QK0_P B_11 P 24 CCIO-P 0
8DQ17QK0_N B_10 N 23 CCIO-N 1
7 DQ16 DQ17 B_09 P 22 CCIO-P 1
6 DQ15 DQ16 B_08 N 21 CCIO-N 1
B 3-state DQ15 B_07 P 20 DQS-P 0 0101
ADMDM B_06 N 19 DQS-N 1 5
5 DQ14 DQ14 B_05 P 18 1
111
1
4 DQ13 DQ13 B_04 N 17 1 F
3 DQ12 DQ12 B_03 P 16 1
2 DQ11 DQ11 B_02 N 15 1
1 DQ10 DQ10 B_01 P 14 1
111
1
0 DQ9 DQ9 B_00 N 13 1 F5FF
Table 3-19: Parameters for Example RLDRAM II Data Byte Lane #3
Parameter Value
DM_MAP 12'h01A
DQTS_MAP 12'h01B
PHY_0_BITLANES 12'h5FF
DATA1_MAP 108'h018_017_016_015_014_013_012_011_010
QK_MAP 8'h01
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Xilinx Zynq-7000 Specifications

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Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English