Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 670
UG586 November 30, 2016
www.xilinx.com
Appendix A: General Memory Routing Guidelines
6. Signal lines must be routed over a solid reference plane. Avoid routing over voids
(Figure A-2).
X-Ref Target - Figure A-2
Figure A-2: Signal Routing Over Solid Reference Plane
UG583_c2_13_050614
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