Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 671
UG586 November 30, 2016
www.xilinx.com
Appendix A: General Memory Routing Guidelines
7. Avoid routing over reference plane splits (Figure A-3).
8. Keep the routing at least 30 mils away from the reference plane and void edges with the
exception of breakout regions (Figure A-2).
X-Ref Target - Figure A-3
Figure A-3: Signal Routing Over Reference Plane Split
UG583_c2_14_050614
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V