Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 672
UG586 November 30, 2016
www.xilinx.com
Appendix A: General Memory Routing Guidelines
9. In the breakout region, route signal lines in the middle of the via void aperture. Avoid
routing at the edge of via voids (Figure A-4).
X-Ref Target - Figure A-4
Figure A-4: Breakout Region Routing
UG583_c2_15_051915
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