Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 69
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
PRBS_EADDR_MASK_POS Sets the 32-bit AND MASK position.
This parameter is used with the PRBS
address generator to shift random
addresses down into the port address space.
The END_ADDRESS value is ANDed with the
PRBS address for bit positions that have a 1
in this mask.
PRBS_SADDR_MASK_POS Sets the 32-bit OR MASK position.
This parameter is used with the PRBS
address generator to shift random
addresses up into the port address space.
The START_ADDRESS value is ORed with the
PRBS address for bit positions that have a 1
in this mask
CMD_PATTERN
This parameter sets the command
pattern circuits to be generated. For
a larger device, the CMD_PATTERN
can be set to “CGEN_ALL.” This
parameter enables all supported
command pattern circuits to be
generated. However, it is sometimes
necessary to limit a specific
command pattern because of
limited resources in a smaller device.
Valid settings for this signal are:
• CGEN_FIXED: The address, burst length,
and instruction are taken directly from the
fixed_addr_i, fixed_bl_i, and fixed_instr_i
inputs.
• CGEN_SEQUENTIAL: The address is
increased sequentially, and the increment
is determined by the data port size.
• CGEN_PRBS: A 32-stage Linear Feedback
Shift register (LFSR) generates
pseudo-random addresses, burst lengths,
and instruction sequences. The seed can
be set from the 32-bit cmd_seed input.
• CGEN_ALL (default): This option turns on
all of the options above and allows
addr_mode_i, instr_mode_i, and
bl_mode_i to select the type of generation
during run time.
Table 1-11: Traffic Generator Parameters Set in the example_top Module (Cont’d)
Parameter Description Value
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V

Summary

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

Introduction

Overview of the DDR3 and DDR2 SDRAM Memory Interface Solution, its architecture, and features.

Features

Highlights enhancements in 7 series FPGA memory interface solutions over earlier families.

Chapter 2: QDR II+ Memory Interface Solution

Introduction

Details the QDR II+ SRAM Memory Interface Solution, its architecture, and usage.

Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions

Introduction

Explains RLDRAM II/III Memory Interface Solutions, covering architecture, usage, and simulation.

Chapter 4: LPDDR2 SDRAM Memory Interface Solution

Introduction

Introduces the LPDDR2 SDRAM Memory Interface Solution, its core components, and features.

Features

Details enhancements in LPDDR2 SDRAM solutions, including performance and hardware blocks.

Chapter 5: Multicontroller Design

Introduction

Describes specifications, supported features, and pinout rules for multicontroller designs.

Chapter 6: Upgrading the ISE/CORE Generator MIG Core in Vivado

Appendix A: General Memory Routing Guidelines