Xilinx Zynq-7000 - Page 71

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 71
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
The command patterns instr_mode_i, addr_mode_i, bl_mode_i, and data_mode_i
of the traffic_gen module can each be set independently. The provided
init_mem_pattern_ctr module has interface signals that allow you to modify the
command pattern in real-time using the Vivado debug logic core virtual I/O (VIO).
This is the varying command pattern:
1. Set vio_modify_enable to 1.
2. Set vio_addr_mode_value to:
1: Fixed_address.
2: PRBS address.
3: Sequential address.
3. Set vio_bl_mode_value to:
1: Fixed bl.
2: PRBS bl. If bl_mode value is set to 2, the addr_mode value is forced to 2 to generate
the PRBS address.
4. Set vio_data_mode_value to:
0: Reserved.
1: FIXED data mode. Data comes from the fixed_data_i input bus.
2: DGEN_ADDR (default). The address is used as the data pattern.
3: DGEN_HAMMER. All 1s are on the DQ pins during the rising edge of DQS, and all 0s are
on the DQ pins during the falling edge of DQS.
4: DGEN_NEIGHBOR. All 1s are on the DQ pins during the rising edge of DQS except one
pin. The address determines the exception pin location.
EYE_TEST
Force the traffic generator to only
generate writes to a single location,
and no read transactions are
generated.
Valid settings for this parameter are “TRUE”
and “FALSE.”
When set to “TRUE,” any settings in
vio_instr_mode_value are overridden.
Notes:
1. The traffic generator might support more options than are available in the 7 series Memory Controller. The settings must
match supported values in the Memory Controller.
Table 1-11: Traffic Generator Parameters Set in the example_top Module (Cont’d)
Parameter Description Value
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