Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 88
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
3. Apply the settings and select OK.
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in Figure 1-47.
5. Vivado invokes IES and simulations are run in the IES tool. For more information, see the
Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 8].
X-Ref Target - Figure 1-50
Figure 1-50: Simulation with IES
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English