Safran CORTEX Series - Coder;Mapper Implementation at 2, 2.25, 2.5 & 2.75 Bits;Channel-Symbol Efficiency; Figure 26: Coder and Mapper Implementation at 2 Bits;Channel-Symbol Efficiency; Figure 27: Coder and Mapper Implementation at 2.25 Bits;Channel-Symbol Efficiency

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 102
Coder/Mapper Implementation at 2, 2.25, 2.5 & 2.75 bits/channel-symbol Efficiency 3.3.7.2.4
The principle of the coder-mapper for 2, 2.25, 2.5, and 2.75 bits/channel-symbol efficiency is given in
next figures:
Figure 26: Coder and Mapper Implementation at 2 bits/channel-symbol Efficiency
Figure 27: Coder and Mapper Implementation at 2.25 bits/channel-symbol Efficiency
Byte to Symbol conversion
Differential
coder
Constellation mapper
x6
w5
x4
x3
x2
w1
Convolutional
Coder R=3/4
x6
x5
x4
x3
x2
x1
x0
Carrier
Generator
Modulated
Carrier
Z
(0)
Z
(1)
Z
(2)
Z
(3)
Data In(0:7)
x7
x7
w8
x8
Byte to Symbol conversion
Differential
coder
Constellation mapper
w6
x5
x4
x3
w2
x1
Convolutional
Coder R=3/4
x6
x5
x4
x3
x2
x1
x0
Carrier
Generator
Modulated
Carrier
Z
(0)
Z
(1)
Z
(2)
Z
(3)
Data In(0:7)
x7
x7
x8
x8
x9
w9