Safran CORTEX Series - Table 3: Data & Clock Outputs Vs Demodulation

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 66
OUTPUT MODE
BPSK
QPSK
8PSK
16QAM
SPLIT 2
QPSK
8PSK
16QAM
I/QMERGE
QPSK
8PSK
16QAM
SPLIT 4
A/UQPSK
CHANNEL A
1
CLK+
CLK-
J10 / J11
Clock @ BR
Demod A
Clock @ BR/2
Demod A
Clock @ BR
Demod A
Clock @ BR /4
Clock @ BR I
Demod A
OUT1+
OUT1-
J12 / J13
Data
Data I
Data
Data I -1
Data I
OUT2+
OUT2-
J14 / J15
Reserved
Data Q
Data
Data Q -1
Data Q
OUT3+
OUT3-
J16 / J17
Clock @ BR
Demod A
Clock @ BR/2
Demod A
Clock @ BR
Demod A
Clock @ BR/4
Clock @ BR Q
Demod A
CHANNEL B
1
CLK+
CLK-
J20 / J21
Clock @ BR
Demod B
Clock @ BR/2
Demod B
Clock @ BR
Demod B
reserved
Clock @ BR I
Demod B
OUT1+
OUT1-
J22 / J23
Data
Data I
Data
Data I - 2
Data I
OUT2+
OUT2-
J24 / J25
Reserved
Data Q
Data
Data Q - 2
Data Q
OUT3+
OUT3-
J26 / J27
Clock @ BR
Demod B
Clock @ BR/2
Demod B
Clock @ BR
Demod B
Reserved
Clock @ BR Q
Demod B
Table 3: Data & Clock Outputs vs Demodulation
* BPSK demodulation can be set to SPLIT2 mode with high rates hardware menus (single demodulator).
In this case the data stream is split on the two outputs J12/ J13 and J22/J23.