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Safran CORTEX Series - Bit Synchronization

Safran CORTEX Series
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HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems IMP000074 e14r1
Page 46
Please note that for link budget with actual satellite that implementation loss doesn’t take into account
imperfections of:
- on board modulator RF and antenna Multipath non-linearity
- non Gaussian transmission imperfection weather
- ground imperfection: pointing accuracy RF & feed..
And for transmission above 300Mbps all those imperfections become critical.
Cortex DEAF and/or XDEAF will correct all those imperfections with residual loss from 0.1 to 1dB.
Bit Synchronization 1.6.1.4
Acquisition range 0.1 % of the symbol rate
PCM code NRZ-L/M/S, BP-L/M/S
Differential decoder DNRZ for QPSK and OQPSK
Eb/No measurement Resolution: 0.1 dB
Accuracy: 1 dB
Symbol clock display Yes
Output ports I Channel : Data & Clock
Q Channel : Data & Clock
Merged I+Q : Data & Clock
Output (electrical) ECL Differential or LVDS
Output clock polarity Normal or inverted
Output data polarity Normal or inverted (+ swap I/Q)

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