Safran CORTEX Series - Accumulated Phase Format

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 112
Accumulated Phase Format 3.3.10.4
Elementary 32-bit phase values are accumulated in a 96-bit internal counter. The phase resolution of
this counter is 2
-32
cycle, or 2π/2
32
radian = 8.4e-8°. The 32 LSB can thus be seen as a measurement
of the phase, modulo 2π, while the 64 LSB count the number of cycles since the Doppler port started to
emit:
A 64 bit counter, using 32 bits for the modulo part, and 32 bits for the cycle counting part, has a
revolution period of 5s for an IF at 720 MHz. The overall 96 bits counter has a revolution period of more
than 800 years. The Doppler port thus discards some of the MSBs and LSBs to output 64 bits phase
measurements. The truncature operates as follows. The registry value:
HKEY_LOCAL_MACHINE\SOFTWARE\IN-SNEC\CrtxHdr\SetDefault\Signal Processing\DmuX\Integ_Phase_BinShift
sets the number of LSBs that are discarded. Let N be the value of Integ_Phase_BinShift:
The phase resolution thus becomes 2π/2
32-N
radian. The revolution period of this counter is 2
32+N
/IF
where IF is the input IF frequency. The default value for the registry key is 15 (decimal), 0xE (hex).
Table 11 and Table 12 give phase resolution and revolution period for different settings of N, with an IF
of 720MHz, and 1.2 GHz.
Samples are stored for further transmission, in a measurement block which size is programmable
between 1 and 1000 elementary measurement(s). The first measurement in the block is time-tagged.
The figure below shows how to set the block size in the DMU window.
2π rad
Cycle counter
64 bits
32 bits
2π rad
Cycle counter
2π rad
Cycle counter
Internal 96 bits counter:
Doppler port phase measurement:
32-N
32+N
N