HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
External Data & Clock (Input Format) 3.6.1.1.3
One should ensure the data & clock timing comply to the CORTEX HDR requirements (see Section
1.6.6 ).
Data-to-clock timing requirements:
Square 180° clock
50% duty cycle (worst case: 45/55)
Tset_time < 1 ns
Thold_time < 0.6 ns
The phase jitter should be as low as possible (< 1 ns). One recommends connecting the input clock
before selecting the External Data mode. In this mode, the external clock must be permanently
provided.
Playback 3.6.1.1.4
Please refer to the dedicated Playback section 3.4.12 .
Internal and External framing 3.6.1.2
The test modulator supports up to two framing layers (see Figure 53: Data Generation Scheme
):
External framing which is the first framing encountered by the data. It can be ON or OFF.
Internal framing which is the second framing encountered by the data, as it immediately follows
the external framing. It can also be ON or OFF.
Both layers are asynchronous.
Framing features 3.6.1.2.1
Each framing supports:
ASM insertion (CCSDS 131.0-B-2, up to 128 bits SW)
Scrambling (CCSDS 131.0-B-2 or custom)
FECF insertion (CCSDS 100.0-G-1, or custom)
NRZ-M encoding
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