Safran CORTEX Series - Table 2: Demodulator I;Os Definition

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 63
DEMODULATOR
CHANNEL B
HW dependant
CLK +
CLK -
J20
J21
Refer to paragraph
(2.2.2.2.1 )
ECL differential
V
+
> -1 Volt, V
-
< -1.7 Volt
Adapted Termination required
(note 1)
OUT1 +
OUT1 -
J22
J23
Refer to paragraph
(2.2.2.2.1 )
OUT2 +
OUT2 -
J24
J25
Refer to paragraph
(2.2.2.2.1 )
OUT3 +
OUT3 -
J26
J27
Refer to paragraph
(2.2.2.2.1 )
DEMODULATOR
INPUT
CLK IN +
CLK IN -
J60
J61
Clock input
ECL differential
V
+
> -1 Volt, V
-
< -1.7 Volt
50  termination required (note 2)
IN1 +
IN1 -
J62
J63
Data input
for BER measurement or
data post-processing
IN2 +
IN2 -
J64
J65
Data input
for BER measurement or
data post-processing
IN3 +
IN3 -
J66
J67
Data input
for BER measurement or
data post-processing
LVDS I/Os
HW dependant
LVDS DEMOD
OUT A
J70
Data and clock outputs
for demodulator A
LVDS standard characteristics
(note 3)
LVDS DEMOD
OUT B
J71
Data and clock outputs
for demodulator B
LVDS DEMOD
IN
J72
Data and clock inputs
LVDS DATA
OUT
J73
For customized
interconnection panel
LVDS DATA IN
J74
For customized
interconnection panel
Table 2: Demodulator I/Os Definition