Safran CORTEX Series - 1.4 CORTEX HDR ARCHITECTURE

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 34
CORTEX HDR Architecture 1.4
Functional Block Diagram of a Demodulation Channel 1.4.1
Figure 1: CORTEX HDR Demodulation and Ingestion Functional Block Diagram
Optional
ingestion:
Frame Synchronization
Time
Tagging
Real Time TCP/IP UDT
Data
Storage
Internal SSD
BER
Measurement
Vector Analysis
Spectrum Analysis
Automatic
filter display
Monitoring & Control
Monitoring & Control
Software Package (MCS)
Graphical
User Interface
(Free Copyright)
Analog Processing
(2 IF inputs)
A/D Conversion
Vector Demodulation
(1 to 8 2
demod
)
BPSK, QPSK,
O/S/U/A/QPSK
SOQPSK 8PSK
16QAM/16…256APSK
Rejection &
Matched filter
I&D
RRC /GMSK / SOQPSK filters
EQUALIZATION
DEAF XDEAF
IF Inputs
Time
&
Frequency
Distribution
5/10 MHz Input
Time Code Input
Ethernet LAN
Bit
Sync
PCM
Decoding
Data +
Clock
Generation
Digital Outputs
Optional
Viterbi
or TCM
decoding
SCSI output
Optional
CADU
RS or LDCP
Decoding
Descrambling
Transport layer