Safran CORTEX Series - Table 14: Modulations and Input Modes; Table 15: Connectors Allocation, Single Ended ECL

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 174
When the board is fitted with differential ECL the only mode available is Serial data mode as only
one data input is available. In this case the serial data mode is forced, regardless of the setting that is
set in the configuration table.
Here are the possible schemes depending on the modulation and the data type:
MODULATION
HARD SYMBOL
(SINGLE ENDED ECL ONLY)
OTHERS
BPSK
Yes, I data
Yes
QPSK
Yes, IQ data
Yes
OQPSK
Yes, IQ data
Yes, single clock, offset
introduced internally to the
modulator.
8PSK
Yes, IQZ data
Yes
16QAM
Yes, IQZX
Yes
16APSK
Yes, IQZX
Yes
32APSK
No
Yes
64APSK
No
Yes
Table 14: modulations and input modes
Here is the table of connector allocation depending on the data scheme, for single ended ECL:
LABEL
ID
HARD SYMBOL
SERIAL
//2 DATA
//3 DATA
//4 DATA
ECL IN 1
J52
I data
(1)
Data
D1
(2)
D1
(2)
D1
(2)
ECL IN 2
J53
Q data
(1)
-
D2
(2)
D2
(2)
D2
(2)
ECL IN 3
J54
Z data
(1)
-
-
D3
(2)
D3
(2)
ECL IN 4
J55
X data
(1)
-
-
-
D4
(2)
ECL IN 5
J56
Clock
Clock
Clock
Clock
Clock
Table 15: connectors allocation, single Ended ECL
(1): I/Q/Z/X data refers to direct symbol mapping. For example, I/Q/Z mode in 8PSK means that each
bit fed to the input will be directly used to map the symbol using the mapping selected in the connected
MDU. In BPSK, only I is relevant. In QPSK/OQPSK, I and Q are relevant. In 8PSK I, Q, and Z are
relevant. In 16APSK and 16QAM, I, Q, Z and X are relevant.
(2): the convention for data merging is D1 D2 D3 D4, D1 being the MSB and first bit transmitted.