HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Constraints 3.6.4.1.5
Some constraints apply to this functionality. They are summarized hereafter.
The maximal clock rate is 400 MHz
The format input can be used only in FPGA menu #1, on the single MDU available.
The data input to the modulator is direct meaning no encoding is available, apart from
differential symbol encoding (DNRZ, NRZ-M…). As an example, RS223 and Viterbi are not
available when using direct input to the modulator.
The clock input is processed in real time to servo control the symbol rate of the modulator. This
means than the clock should be stable, hole less. Good behavior in other contexts is not
guaranteed.
UQPSK and GMSK modulations are not supported.
DVB-S2 and SCCC are also not supported.
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