Safran CORTEX Series - BER Measurements

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 145
QPSK – 4 DPU, DPU Map = 0
Bit number
odd-b1
even-b1
odd-b2*
even-b2*
DPU-X
DPU-A
DPU-C
DPU-E
DPU-G
Offset (bytes)
0
1
2
3
QPSK – 4 DPU, DPU Map = 1
Bit number
odd-b1
odd-b2
even-b1
even-b2
DPU-X
DPU-A
DPU-C
DPU-E
DPU-G
Offset (bytes)
0
4
1
5
QPSK – 2 DPU, DPU Map = 0 (No ambiguity resolution process)
Bit number
b1
b2
DPU-X
DPU-A
DPU-C
Offset (bytes)
N/A
N/A
QPSK – 2 DPU, DPU Map = 1
Bit number
b1
b2
DPU-X
DPU-A
DPU-C
Offset (bytes)
0
4
BER measurements 3.4.13.3
The BER can be done at the DMU (Demodulator Unit) outputs and at each DPU (Data Processing)
output. The BER can be done at different levels inside the DPU by enabling or not the different
operations (Differential encoder/decoder, Frame synchronizer, CCSDS encoder/decoder).