HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Figure 73: 100 Mbps, QPSK direct input setting
BER estimation 3.6.4.1.3
The format input enable BER estimation directly after sampling at the interface. Two BER modes can
be selected:
Merged: data of all parallel bits is merged into a single stream before PRBS comparison.
In hard symbol mode, the merge logic is IQ, IQZ or IQZX, I being the first bit, X the last. In
parallel data mode, the logic is D1 D2, D1 D2 D3 or D1 D2 D3 D4.
Split: BER estimation is performed independently for each input connector. The number of
connectors depends on the operating mode detailed earlier. Some examples are 8PSK, hard
symbol mode (IQZ), or Any modulation with Data //4 (D1 D2 D3 D4).
The following PRBS testers are available: PRBS 7, 10, 11, 15, 23 and 31. The PRBS testers work in
the same manner as the DMU and DPU BER estimators. They can be reset by issuing the correct extra
command or by clicking the ‘0’ button in the main GUI.
Note: only merged mode is available if modulator board is fitted with differential ECL.
MCS preset files 3.6.4.1.4
The following MCS files have been preset and can be used as a base for customization, in the
D:\ZDS\Data\HDR\MCS\DefaultConfig\Test\IO Boards\Standard\Modulator folder
ECL_serial_in_QPSK.mcs:
o QPSK, 100 Mbps, 720 MHz carrier, DNRZ with 1 bit data + clk @ 100 MHz
ECL_serial_in_8PSK.mcs:
o 8PSK, 100 Mbps, 720 MHz carrier, NRZ-L with 1 bit data + clk @ 100 MHz
ECL_IQ_in_QPSK.mcs:
o QPSK, 200 Mbps, 720 MHz carrier, DNRZ with I/Q + clk @ 100 MHz
ECL_IQZ_in_QPSK.mcs:
o 8PSK, 300 Mbps, 720 MHz carrier, NRZ-L with I/Q/Z + clk @ 100 MHz
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