Safran CORTEX Series - Figure 187: Playback LAN: Reset Playback Client Button in TCP-IP Clients Window; Figure 188: Playback LAN: Acquisition and Stop All Buttons in the Toolbar

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HIGH DATA RATE RECEIVER

HDR-4G+ USER’S MANUAL

Ref. DTU 100782

Is.Rev 3.5

Date: June 1, 2021

This document is the property of Safran Data Systems.

It cannot be duplicated or distributed without expressed written consent.

Page 348

Figure 187: Playback LAN: “Reset playback client” button in “TCP-IP Clients” window

Figure 188: Playback LAN: “Acquisition” and “Stop All” buttons in the toolbar

Main Page

Table of Contents3
Symbols Description22
Ce Marking23
Weee Directive24
Caution24
Important Safety Instructions25
General25
Grounding & Electrical Installation Standards25
Risk of Electric Shocks26
Installation, Environment27
Esd Protective Measures27
Cleaning, Maintenance28
International Security Statements28
Cortex Hdr Overview29
Scope29
Cortex Hdr Main Features30
Mission of the Cortex Hdr31
Introduction31
Operating Modes31
Telemetry Demodulation32
Telemetry Processing32
Polarization and Antenna Combining33
Simulation & Self-Testing33
Cortex Hdr Architecture34
Functional Block Diagram of a Demodulation Channel34
Figure 1: CORTEX HDR Demodulation and Ingestion Functional Block Diagram34
Functional Block Diagram of a Modulation Channel35
Figure 2: CORTEX HDR Test Modulator Functional Block Diagram (Single Channel, Single IF)35
Figure 3: CORTEX HDR Test Modulator - Multi Channel, Multi if Operation35
CORTEX HDR Hardware Architecture36
Figure 4: CORTEX HDR Hardware Block Diagram36
PC-Compatible Workstation37
Figure 5: Example of CORTEX HDR Workstation37
Test Modulator Board38
Demodulator Board38
I/O Connectors38
CORTEX HDR Software39
Local or Remote M&C39
Password Protection39
Software Version40
Figure 6: MCS Software Version40
Cortex Hdr Interfaces41
Mechanical & Electrical Interfaces41
Ethernet TCP-IP Interface41
Table 1: CORTEX HDR TCP-IP Port Addresses41
FTP Interface42
Figure 7: CORTEX HDR TCP-IP Interfaces42
Cortex Hdr Performances43
Demodulation Unit43
IF Reception43
Demodulation44
Implementation Loss45
Bit Synchronization46
Filtering47
Viterbi Convolutional Decoding48
Viterbi ½48
Viterbi ¼48
Scrambler49
Transport Layer (RS-DVB or Asynchronous LDPC Layer)49
Bem 4D 8Psk Tcm Dvb-S R-S50
VHR-DVB-S2 and CCSDS-SCCC Standard50
OQPSK/8PSK Variable Modulation50
Diversity Combining Unit and Antenna Combining51
Data Processing Unit51
Frame Synchronization51
Data Time-Tagging51
CRC Frame Checking51
CCSDS and ECSS Decoding52
LDPC Decoding52
Data Output52
Data Storage53
Playback54
Test Modulator54
IF Modulation54
Noise Source54
Modulation54
PCM Simulation55
Doppler Simulation55
Start-Up Menus55
Frequency Reference56
External Reference56
Internal Reference56
Time Code Reference56
Mechanical - Environment56
Supply57
Hardware Description58
Cortex Hdr Integration58
Hardware Configuration58
PC-Compatible Workstation58
Demodulator Board59
Overview59
Separate if Inputs59
Figure 8: Demodulator Input Stage with Separate if Inputs59
Test Modulator Board60
Figure 9: CORTEX HDR Test Modulator - Multi Channel, Multi if Operation60
I/O Connectors Definition61
CPU Board I/Os61
Demodulator & Test Modulator I/Os61
HDR 4G/4G+ I/Os61
Figure 10: CORTEX HDR 4G/G+ I/Os61
Demodulator I/Os62
Table 2: Demodulator I/Os Definition63
Channel a & Channel B I/Os Description65
Table 3: Data & Clock Outputs Vs Demodulation66
Table 4: Data & Clock CADU Outputs67
Table 5: Data & Clock Outputs Vs Demodulation (Soft Outputs) Hardware Menu Dependent67
Figure 11: Soft Decision Coding Vs I/Q Constellation (Normal Soft Output)68
Figure 12: Soft Decision Coding Vs I/Q Constellation (Merge Soft Output)69
AIT Connector (LVDS Data Output - J73) Description70
Table 6: Data and Clock Outputs on J7370
Demodulator Inputs Description71
Table 7: Single Channel Demodulator Input Modes71
Table 8: Dual Channel Demodulator Input Mode71
Test Modulator I/Os72
Table 9: Modulator I/Os Definition72
Output Data Definition and Timing73
Timing for All Output Types73
I/Q Merged Output74
Split 2 Output (I and Q Normal Output)74
Split 4 Output75
CADU Output Formats75
Specific I/Os (Customers Requirements)76
Functional Description77
Monitoring & Control77
Monitoring77
Control77
Logging77
Demodulation78
IF Processing78
Bit Synchronization78
Signal Processing78
Customized FIR Filters79
General79
Custom Filters Programming79
DEAF Filtering80
General80
Principle of the DEAF81
Use of the DEAF81
Figure 13: Effect of the DEAF82
XDEAF for Reception of Dual Polarization Data Transmission83
Adjacent Channel Rejection85
Figure 14: Effect of the XDEAF85
Viterbi Convolutional Decoding86
General86
Single or Dual Viterbi Decoder87
Figure 15: Viterbi Decoding Module. Single & Dual Operating Modes87
Parallel Viterbi Decoders88
Figure 16: Parallel Viterbi Decoding Module88
Punctured Viterbi89
Figure 17: Viterbi De-Puncturing Process89
Figure 18: Punctured Viterbi BER Performances90
PCM Decoding91
DNRZ, QPSK Decoding (DQPSK)91
CCSDS Recommended DNRZ Code in QPSK Mode91
Other Possibilities for DNRZ Codes in QPSK Mode92
DQPSK Configuration92
DNRZ, OQPSK Decoding93
Most Commonly Used DNRZ Code in OQPSK Mode93
Other Possibilities for DNRZ Codes in OQPSK Mode94
DOQPSK Configuration94
I/Q Shift Compensation in OQPSK Mode95
CCITT V.35 De-Scrambler95
BEM: 4D-8PSK-TCM-DVB-S Reed Solomon Decoding95
Introduction95
8PSK-TCM Coder96
Differential Coder97
Figure 19: Structure of the 4D 8PSK-TCM Coder/Mapper97
Table 10: Bit Mapping for Differential Coder97
Convolutional Coder98
Figure 20: Differential Coder and Modulo-8 Adder Principle98
Figure 21: Convolutional Coder Recommended for High Data Rates98
Constellation Mapper for 4D-8PSK-TCM99
Figure 22: Constellation Mapper for 2 Bits/Channel-Symbol99
Figure 23: Constellation Mapper for 2.25 Bits/Channel-Symbol100
Figure 24: Constellation Mapper for 2.5 Bits/Channel-Symbol101
Figure 25: Constellation Mapper for 2.75 Bits/Channel-Symbol101
Coder/Mapper Implementation at 2, 2.25, 2.5 & 2.75 Bits/Channel-Symbol Efficiency102
Figure 26: Coder and Mapper Implementation at 2 Bits/Channel-Symbol Efficiency102
Figure 27: Coder and Mapper Implementation at 2.25 Bits/Channel-Symbol Efficiency102
Figure 28: Coder and Mapper Implementation at 2.5 Bits/Channel-Symbol Efficiency103
Figure 29: Coder and Mapper Implementation at 2.75 Bits/Channel-Symbol Efficiency103
DVB-S Transport Layer: Reed Solomon Code104
Synchronized Randomization104
Figure 30: Concatenation Principle104
Reed-Solomon Encoding105
Packets Interleaving and Synchronization Byte Insertion105
Figure 31: Randomization Principle105
Interface between Trellis Coded Symbols and Bytes107
Figure 32: Data Arrangement in TCM 2.5 Bits/Channel_Symbol107
PRN-BER Computation108
BER on Separate I & Q Channels108
BER on Merged I & Q Channels108
Digital Outputs109
Figure 33: BER Measurement Methods: Tested Ambiguities and GUI Display109
Doppler and Integrated Phase Measurement110
Introduction110
Required Setup for Optimal Performance110
Sampling Rate111
Accumulated Phase Format112
Table 11: Counter Capacity and Resolution at 720Mhz113
Table 12: Counter Capacity and Resolution at 1.2Ghz114
Displaying the Carrier Offset of the Doppler Port in the DMU Window115
Interpolation Process116
Doppler Computing116
Impact of Phase Errors on Doppler Computing117
Sampling Period Resolution117
Error Due to Computing117
Error Due to Floating Representation118
Es/N0 Estimators in DVB-S2 and SCCC Environment118
Warning118
Standard Es/N0 Estimation118
Figure 34: Typical Es/N0 Estimation over the Constellation118
Figure 35: Estimator Behavior VS Es/N0 and Modulations119
Figure 36: Standard Es/N0 Estimate in the GUI119
Data-Aided Es/N0 Estimation in SCCC and DVB-S2120
Figure 37: Standard Es/N0 Estimate in the Vector Pane120
Figure 38: Data-Aided Estimation of Es/N0121
Figure 39: Data-Aided Estimator in the GUI, Physical Layer Pane of the Demodulator122
Data Processing123
Functional Breakdown of the Data Processing Unit123
Figure 40: Data Processing Unit Block Diagram123
Frame Synchronization & Ambiguity Resolution124
Frame Synchronization Strategy124
Figure 41: Frame Synchronization Process125
CCSDS Data De-Randomizer126
Customized Data De-Randomization127
CRC Frame Checking128
(255,223) Reed-Solomon Decoding128
(255,239) Reed-Solomon Decoding129
(10,6) Reed-Solomon Frame Header Decoding129
Specific Decoding129
LDPC Decoding130
Introduction130
LDPC 7/8 for Near-Earth Applications130
AR4JA LDPC ½, 2/3, 4/5 Codes for Deep Space Applications130
Implementation130
Performances131
Recording and Data Transmission over Ethernet131
General Consideration131
Data Storage131
TCP-IP Data Recovery132
Figure 42: Data Transmission over TCP-IP. Message Formatting132
Archiving and FTP Recovery133
Generality133
Overview133
Data Files Structure134
Report Files Structure134
Figure 43: Recorded Data File Structure134
Standard FTP CCSDS Mode135
Figure 44: CCSDS FTP Mode Storage Directories136
FTP User Defined Mode137
Playback Function138
Operating Modes138
Figure 45: Playback Function: Test Modulator Operating Mode138
Figure 46: Playback Function: Test Modulator Data + Clock Mode138
Sources of the Data to Replay139
Multi-DPU Processing139
Generality139
Figure 47: QPSK Demodulation with 2 DPU140
Figure 48: QPSK or 16QAM Demodulation with 4 DPU141
Figure 49: 16QAM Demodulation with 8 DPU142
Figure 50: QPSK or 16QAM Demodulation with 1 DPU143
Figure 51: QPSK Demodulation with 2 DPU143
Ambiguity Resolution by the Dpus144
Figure 52: 8 DPU Data Flow for Automatic Ambiguity Resolution144
BER Measurements145
Data Output146
Guide for Multi DPU Operation147
Polarization Combining152
General152
Data Path152
Signal Processing153
Test Modulation155
Data Generation155
Data Sources155
Pseudo Random Data155
Figure 53: Data Generation Scheme155
Data from File156
File Format156
Cycle Length156
Figure 54: 10-Bit Generator with Feedbacks after Register 3 and 0156
Table 13: PRBS Generators for BER Analysis156
External Data & Clock (Input Format)157
Playback157
Internal and External Framing157
Framing Features157
Framing and Cycle Length158
Encoding158
Scrambling158
Figure 55: Frame Aligned with File158
Fecf159
Modulation Unit159
Main Features159
Constellation Mapping159
Figure 56: 16APSK Mapping 1162
Figure 57: 16APSK Mapping 2162
DNRZ Coding164
Multi-DGU Support165
Figure 58: Example of 2 Dgus Merging for Simulation of Independent I/Q Transmission in QPSK165
Figure 59: Example of 3 Dgus Merging for Simulation of Independent I/Q/C Transmission in 8PSK166
Figure 60: Example of 3 Dgus with Different Offsets166
Dvb-S2 & Sccc167
IF Signal Generation167
IF1 and IF2167
Figure 61: if Signal Generation168
Figure 62: GUI: if Unit169
Figure 63: Example 1: 2 Adjacent Channels on IF1 - 1 Single Channel on IF2170
Figure 64: Example 1: 2 Adjacent Channels on IF1 - 1 Single Channel on IF2 (GUI)170
Figure 65: Example 2: 3 Adjacent Channels on IF1 - Nothing on IF2171
Figure 66: Example 2: 3 Adjacent Channels on IF1 - Nothing on IF2 (GUI)171
Figure 67: Example 3: 1 Channel on IF1 - 1 Channel on IF2172
Figure 68: Example 3: 1 Channel on IF1 - 1 Channel on IF2 (GUI)172
Doppler173
Modulation of External Data173
Direct Input to the Modulator173
Principle173
Figure 69: ECL Inputs on Test Modulator Board - Single Ended ECL173
Figure 70: ECL Inputs on Test Modulator Board - Differential ECL173
Table 14: Modulations and Input Modes174
Table 15: Connectors Allocation, Single Ended ECL174
Figure 71: IQZ Mapping Example175
Table 16: Connectors Allocation, Differential ECL175
Configuring the Modulator and the Format Input176
Figure 72: Direct Modulator Input, as Seen in the Main Modulator Window176
BER Estimation177
MCS Preset Files177
Figure 73: 100 Mbps, QPSK Direct Input Setting177
Constraints178
Cable Equalizer Filter179
Figure 74: Example of Non-Linearity in a RG188A/U Cable179
Figure 75: Example of Cable Compensation180
Data Logging181
Standard Loging181
Extended Logging182
System Logging184
Operating Manual185
Starting and Configuring the Cortex Hdr185
First Steps185
Starting the PC Workstation185
Signal Processing Software. Start-Up Menu185
Starting the Monitoring & Control Software185
Factory Configuration185
Software Exit & CORTEX HDR Shutdown186
Exiting the Monitoring & Control Software186
Exiting the Signal Processing Software186
Restarting the SPS & MCS186
CORTEX HDR Shutdown186
Screen Saver186
Signal Processing Software (Sps)187
CTX Documents187
SPS Start Sequence187
Figure 76: SPS Start Sequence187
Configuring the CORTEX from CTX Documents188
CTX Document Name Table188
CTX Document Storage and Loading188
Start-Up Menu Selection by Remote Access Control (RAC)189
General189
Figure 77: CTX Document Management189
MCS Graphical User Interface190
Figure 78: MCS Menu Management Window190
Menus Description File191
CORTEX HDR-4G Licenses and Basic Menus192
Table 17: the Basic Demodulator Menus of the CORTEX HDR194
Table 18: the Basic Test Modulator Menus of the CORTEX HDR196
4G / XXL / XL Demodulator Menus Equivalence197
XL with XXL and 4G197
XXL with 4G198
4G / XXL Test Modulator Menus Equivalence201
SPS Version Identification202
Common Data202
CORTEX HDR Specific Data202
Figure 79: about CORTEX SPS Version202
CORTEX HDR System Parameters in Registry203
CORTEX Station203
Menus Description203
Last Used Menu203
RAC Port Number203
Demodulation Unit203
Output Clock ON/OFF203
Punctured Viterbi Setting204
BER on Merged or Separate I/Q204
High Ebno Tracking Mode204
I/Q Synchronization in Capture Mode (Menu # 7)204
DNRZ PCM Decoding (Deprecated)205
OQPSK (SQPSK) Algorithm205
DVB-S2 Randomization Polynomial205
Transport Layer: Frame Synchronizer Setting205
Check to Lock Strategy (CTL) for RS DVB205
Lock to Search Strategy (LTS) for RS DVB206
Synchronization Threshold (SYN) for RS DVB206
Synchronization Word for RS DVB206
Idle Synchronization Word for RS DVB206
Frame Size for RS DVB206
Control of the R-S DVB Decoding Chain for RS DVB207
Check to Lock Strategy (CTL) for LDPC207
Lock to Search Strategy (LTS) for LDPC207
Synchronization Threshold (SYN) for LDPC207
Derandomization for LDPC207
Synchronization Word LSB for LDPC207
Synchronization Word MSB for LDPC208
Synchronization Mask LSB for LDPC208
Synchronization Mask MSB for LDPC208
Synchronization Word Length for LDPC208
Decoder Refresh Period208
Transport Layer Status209
Test Modulation Unit209
Selecting the DNRZ Code in QPSK and OQPSK Modulation Mode209
Global HDR209
Selecting LVDS / ECL Inputs of the Test Modulator209
Recording in Raw Data Mode209
DMX Table210
TCP/IP Data Transmission210
TCP/IP Playback Data Reception210
Monitoring & Control Software (Mcs)211
General211
MCS Documents211
MCS Start Sequence. MCS Control Status212
Figure 80: MCS Start Sequence212
M&C Session. MCS Documents Management214
Close the Active M&C Session214
Open an M&C Session with a CORTEX214
Save the CORTEX Configuration to an MCS Document on the Disk214
Reconfigure the CORTEX from an Existing MCS Document214
Graphical User Interface215
MCS Login Window215
Figure 81: MCS Top-Level Window215
Figure 82: MCS Login Window215
MTDI (Multiple Tabbed Document Interface)216
Figure 83: Multiple Tabbed Document Interface216
Upper Toolbar217
Common Data217
Lower Toolbar219
Common Data219
CORTEX HDR Specific Data220
Bottom Status Toolbar221
CORTEX Monitoring & Configuration221
Default Operating Mode221
CORTEX Configuration221
Forced Connection to the Control Port (Pseudo Local Mode)222
OK/DIFFER Management Mode222
Standard Mode222
Protected Mode223
Automatic Mode223
MCS Version Identification224
Changing a Password224
Figure 84: Cortex MCS About: Software Version224
MCS Interface for CTX Document Management225
Figure 85: Changing a Password225
MCS Interface for User MCS Files Loading226
MCS File System Architecture227
MCS System Parameters in Registry227
Monitoring227
Monitoring Rate227
MCS Auto-Connect227
Auto Connect ON/OFF227
Auto Connect Time-Out228
Auto Connect Retry228
MCS Preferences228
Synchronization Word: Bit Masking Convention228
Operating System and Files Architecture229
Introduction229
Files Architecture229
Files Associated with Monitoring & Control Software229
Files Associated with the Signal Processing Software229
Files Associated with the Cortex HDR Hardware230
Other Files230
Windows 7 Tools & Functionalities230
Cortex Hdr Gui232
Conventions &Warnings232
Graphical User Interface. Windows Breakdown233
Figure 86: Graphical User Interface: Windows Breakdown233
CORTEX HDR Top-Level Windows234
Global" Window234
CORTEX HDR Architecture & Global Status234
Figure 87: CORTEX HDR: Global Window234
Global Engineering Window236
Figure 88: Global Engineering Window236
TCP-IP Secondary Window237
Figure 89: TCP-IP Secondary Window237
Time" Window238
Figure 90: CORTEX " Time " Window238
Control239
Monitoring239
NTP Cilent Set-Up239
Time Management Procedures240
Loss of Time Code or Time Code Missing240
Leap Second Management240
Figure 91: Leap Second Management241
Absolute Time Reference242
Absolute Reference Time & Leap Second Management243
Config" Window244
Control244
Figure 92: CORTEX HDR: Config. Window244
Figure 93: Configuration Help Window for the Demodulator246
Figure 94: Configuration Help Window for the Test Modulator246
Monitoring247
Project" Window248
Control248
Monitoring248
Figure 95: CORTEX HDR: Project Window248
Information" Window249
Figure 96: CORTEX HDR: Information Window249
Mod" Window250
Figure 97: "Mod" Window250
Modcnf" Window251
Figure 98: "Modcnf" Window251
Demodulator Windows252
Global" Window252
Figure 99: Demodulator: Global Window for QPSK Modulation + I & D Filter252
Figure 100: Demodulator: Global Window for QPSK Modulation + Raised Cosine Filter252
Figure 101: Demodulator: Global Window for QPSK Modulation + Custom Filter253
Figure 102: Demodulator: Global Window for OQPSK Modulation253
Figure 103: Demodulator: Global Window for GMSK Modulation254
Figure 104: Demodulator: Global Window for SOQPSK Modulation254
Figure 105: Demodulator: Global Window for UQPSK Modulation255
Figure 106: Demodulator: Global Window for 8PSK Modulation255
Figure 107: Demodulator: Global Window for 16QAM Modulation256
Figure 108: Demodulator: Global Window for 16APSK Modulation256
Figure 109: Demodulator: Global Window for 32APSK Modulation257
Figure 110: Demodulator: Global Window for 64APSK Modulation257
Figure 111: Demodulator: Global Window for VCM QPSK / 8PSK258
Figure 112: Demodulator: Global Window for DVB-S2 /SCCC258
Figure 113: Demodulator: Global Window for Multi-DPU Operation259
Control260
IF Processing260
Flow ID. (Hex)265
Matched Filter265
Optional Rejection Filter266
Monitoring266
Upper Banner266
Other Status & Alarms267
Physical Layer" Window268
Figure 114: Demodulator: Physical Layer Window for SCCC and DVB-S2 Standard268
Control269
Monitoring270
Physical Layer Status" Window271
Monitoring271
Figure 115: Demodulator: Physical Layer Status Window for SCCC and DVB-S2 Standard271
BER" Window272
Figure 116: Demodulator: BER Window PRN Mode272
Figure 117: Demodulator: BER Window File Mode272
Control273
Monitoring273
Upper Banner273
Other Status & Alarms273
Decoding" Window275
Figure 118: Demodulator: Decoding Window for BPSK Modulation275
Figure 119: Demodulator: Decoding Window for QPSK & OQPSK Modulation (Viterbi Single)275
Figure 120: Demodulator: Decoding Window for QPSK & OQPSK Modulation (Viterbi Dual)276
Figure 121: Demodulator: Decoding Window for UQPSK Modulation276
Figure 122: Demodulator: Decoding Window for 8PSK Modulation277
Control278
Monitoring280
Upper Banner280
Other Status & Alarms280
Spectrum" Window281
Figure 123: Demodulator: Spectrum Window281
Vector" Window283
Figure 124: Demodulator: BPSK Vector Window283
Figure 125: Demodulator: QPSK(OQPSK) Vector Window284
Figure 126: Demodulator: 8PSK Vector Window284
Figure 127: Demodulator: 16QAM Vector Window285
Figure 128: Demodulator: 16APSK Vector Window285
Figure 129: Demodulator: 32APSK Vector Window286
Filter" Window287
Figure 130: Filter: Time Display Selection287
Figure 131: Filter: Frequency Display Selection288
Data Processing Unit Windows290
CADU" Window290
Control290
Figure 132: DPU: CADU Window290
Monitoring294
Upper Banner294
Frame Synchronizer Status294
Reed Solomon Decoders Status294
LDPC Status295
CRC Status295
Control (Transport Layer Window)296
Figure 133: DPU: Transport Layer Window (R-S DVB Mode)296
Monitoring (Transport Layer Window)297
BER" Windows297
Figure 134: DPU: BER Window297
Control298
Monitoring298
Real Time Frame" Window299
Control299
Figure 135: Data Processing Unit: Real Time Frame Window299
Monitoring300
TCP-IP Status300
Frame Sync. Status300
Upper Banner300
Quick Look" Window301
Control301
Figure 136: Data Processing Unit: Quick Look Window301
Telemetry Blocks Quick Look302
Figure 137: Telemetry Block Description302
Monitoring303
Upper Banner303
Polarization Combining Windows304
Global" Window304
Control304
Figure 138: Polarization Combining: Global Window304
Monitoring305
Other Status and Alarms306
BER" Window306
Decoding" Window306
Vector" Window306
Data Recording Unit Windows307
Global Disk and Memory Management" Window307
Figure 139: Global Disk & Memory Management Window (Configuration)307
Figure 140: Global Disk & Memory Management Window (Status)307
Control308
Monitoring311
Recording Global" Window312
Control312
Figure 141: DRU: Recording Global Window312
Monitoring314
Upper Banner314
Recorder Status314
FTP" Window315
Figure 142: DRU: FTP Window (Generic)315
Control316
Figure 143: DRU: FTP Window (CCSDS Standard)316
Monitoring318
Session Status318
Upper Banner318
Virtual Channels" Window319
Control319
Monitoring319
Virtual Channels Information319
Upper Banner319
Figure 144: DRU: Virtual Channels Window319
Test Modulator Windows320
Data Generation Unit" Windows320
Data" Window320
PRN Selection320
Figure 145: PRN Selection320
File Selection321
File I/Q Selection321
Figure 146: File Selection321
Figure 147: File I/Q Selection321
Control322
Internal Framing" Window322
General Selection322
Figure 148: Internal Framing Window322
Control323
External Framing" Window324
General Selection324
Control324
Figure 149: External Framing Window324
Status & Warnings325
Modulation Unit" Windows325
Modulation" Window325
Bpsk/Qpsk/Gmsk325
Figure 150: Pointing at an Error325
Figure 151: BPSK/QPSK/GMSK Configuration325
Oqpsk326
Uqpsk326
Figure 152: OQPSK Configuration326
Figure 153: UQPSK Configuration326
8Psk327
16Qam327
Figure 154: 8PSK Configuration327
Figure 155: 16QAM Configuration327
16Apsk328
Figure 156: 16APSK Configuration328
Figure 157: 32APSK Configuration328
64Apsk329
Viterbi Mode329
Figure 158: 64APSK Configuration329
Figure 159: Viterbi Configuration329
TCM Mode330
Control330
Figure 160: TCM Configuration330
Physical Layer" Window332
SCCC Mode332
DVB-S2 Mode332
Figure 161: SCCC Configuration332
Figure 162: DVB-S2 Configuration332
Control333
Status & Warnings333
Figure 163: Status: Input of the MDU333
Figure 164: Modulation Type334
Figure 165: Pointing at an Error334
IF Unit" Windows335
IF" Window335
General Selection335
Control335
Figure 166: if Window335
Doppler/Xpol" Window336
Doppler Configuration336
XPOL Configuration: Still336
Figure 167: Doppler Configuration336
Figure 168: XPOL Configuration: Still336
XPOL Configuration: File337
Control337
Figure 169: XPOL Configuration: File337
Status and Warnings339
Figure 170: if Warnings339
Figure 171: Eb/N0 Status339
Figure 172: Doppler Status339
Figure 173: XPOL Status339
Format Input" Windows340
Format Input" Window - Merged BER340
Figure 174: Serial Data340
Figure 175: Data //4340
Format Input" Window -SPLIT BER341
Figure 176: Hard Symbol, BPSK341
Figure 177: Hard Symbol, OQPSK/QPSK341
Figure 178: Hard Symbol, 8PSK342
Figure 179: Hard Symbol, 16APSK/16QAM342
Control343
Figure 180: Data //4343
Status & Warnings344
Error Insertion344
Figure 181: Status: Clock Status, Locked and Unlocked344
Figure 182: Clock and Raw Bitrate Estimates344
Figure 183: BER and Errors Status344
Figure 184: Pointing at an Error344
Playback Windows345
Global" Window345
Configuration and Control345
Figure 185: Playback: Global Window345
Status346
Specific Operating Mode: Playback LAN347
Figure 186: Playback LAN: Global Window347
Figure 187: Playback LAN: "Reset Playback Client" Button in "TCP-IP Clients" Window348
Figure 188: Playback LAN: "Acquisition" and "Stop All" Buttons in the Toolbar348
File" Window349
Figure 189: Playback: File Window in Report TM Mode (by Date)349
Figure 190: Playback: File Window in Report TM Mode (by Number)349
Figure 191: Playback: File Window in Playback Data File Mode350
Figure 192: Playback: File Window in BER File Mode350
Figure 193: Playback: File Window in Recorded Frames Mode351
Figure 194: Playback: File Window in Playback LAN Mode351
Configuration352
File Selection353
Specific Operating Mode: Playback LAN354
Figure 195: Playback LAN: Overrun Option354
Logging Windows355
Data Logging Control" Window355
Control355
Status355
Figure 196: Logging Status Window355
Data Logging Editor" Window356
Figure 197: Logging Editor Window356
Extended Logging Windows358
Maintenance Procedures359
General359
Mechanical Inspection and Cleaning359
Handling Precautions359
CPU Load Considerations359
Software Loading359
Functional Investigation360
Demodulator Check360
Viterbi Check360
Demodulator Output Ports360
Interpretation of the Vector Display361
Hardware Investigation & Repair366
LED Indicators366
Test Modulator Board366
Demodulator Board366
CPU Board366
Ipmimonitor Tool. Temperature Alarm366
PC Workstation Maintenance367
Software Upgrade & Installation368
Loading or Upgrading the IN-SNEC Software368
Complete Software Re-Installation368
Satellites Configuration Examples369
Annex 1: Cortex Hdr Ethernet Interface378
Annex 2: Demodulator Board379
Annex 3: Test Modulator Board380
Annex 4: Pc-Compatible Workstation381
Annex 5: Project-Specific Data382

Safran CORTEX Series - Figure 187: Playback LAN: Reset Playback Client Button in TCP-IP Clients Window; Figure 188: Playback LAN: Acquisition and Stop All Buttons in the Toolbar

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