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Safran CORTEX Series - Framing and Cycle Length; Encoding; Scrambling; Figure 55: Frame Aligned with File

Safran CORTEX Series
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HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems IMP000074 e14r1
Page 158
Framing and Cycle Length 3.6.1.2.2
When data are generated from a file, if the Cycle Length is compatible with the frame length i.e. if the
actual number of user data needed for each frame (thus excluding the Synchronization Word, the
Parity bits and the FECF) is equal to the Cycle Length, the first bit of the file is the first user bit of the
frame.
Figure 55: Frame aligned with File
Encoding 3.6.1.2.3
Data encoding is possible at the internal framing level. The following encoders are supported
(according to CCSDS 131.0-B-2):
RS (223,255), and RS (239,255)
LDPC (8160,7136) or “NASA-shortened”. This code is known as LDPC 7/8 in the GUI.
LDPC 1/2, 2/3, 4/5 with frame sizes of 1024, 4096 and 16384 bytes
DVB and DVB DSNG
The test unit supports all the features of the demodulator. Please refer to section 3.4 for more
detailed presentation of the supported features.
Due to their “modulation scheme” nature, DVB-S2 and SCCC are described in the Modulation chapter.
Scrambling 3.6.1.2.4
In addition to the CCSDS Scrambling, the Scrambling can be entirely customized in terms of:
Initialization
Generator polynomial
Offset (in bits)
When the offset is set to a non-zero value n, it means that the scrambling process is reinitialized n bits
after the beginning of the frame.
ASM User Data Parity
Cycle Length
Frame Length
Beginning of the File

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