Safran CORTEX Series - Test Modulator I;Os; Table 9: Modulator I;Os Definition

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 72
Test Modulator I/Os 2.2.2.3
All I/O connectors are SMA:
I/O SECTION
LABEL
ID
SIGNAL DEFINITION
ELECTRICAL
IF OUT 1
J50
IF output
-5 to –50 dBm
IF OUT 2
J51
IN1
IN2
IN3
IN4
IN5
J52
J53
J54
J55
J56
Data input (note 1)
Single ended ECL
> -0.81 V for high level
< -1.95 V for low level
ECL termination -2V, 56  included
(Not used in this version)
10 MHz IN
J57
Input Reference Clock
10 MHz, sine or square, 50 
0.5 to 10 Vpp (if DC = 0)
DC max =  4 V
MOD EXT IN 1
J58
IF Input of test mod
Up-converter 1
Optional
0 dBm
MOD EXT IN 2
J59
IF Input of test mod
Up-converter 2
Optional
0 dBm
MOD EXT OUT 1
J36
IF Output of test mod
Up-converter 1
Optional
-10 to –40 dBm
MOD EXT OUT 2
J37
IF Output of test mod
Up-converter 2
Optional
-10 to –40 dBm
Table 9: Modulator I/Os Definition