Safran CORTEX Series - Page 19

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 19
LIST OF TABLES
Table 1: CORTEX HDR TCP-IP Port Addresses ............................................................................................................... 41
Table 2: Demodulator I/Os Definition ................................................................................................................................. 63
Table 3: Data & Clock Outputs vs Demodulation ............................................................................................................... 66
Table 4: Data & Clock CADU Outputs ............................................................................................................................... 67
Table 5: Data & Clock Outputs vs Demodulation (soft outputs) Hardware menu dependent ............................................. 67
Table 6: Data and Clock outputs on J73 .............................................................................................................................. 70
Table 7: Single channel demodulator input modes .............................................................................................................. 71
Table 8: Dual channel demodulator input mode .................................................................................................................. 71
Table 9: Modulator I/Os Definition ..................................................................................................................................... 72
Table 10: Bit Mapping for Differential Coder ..................................................................................................................... 97
Table 11: Counter capacity and resolution at 720MHz ..................................................................................................... 113
Table 12: Counter capacity and resolution at 1.2GHz ....................................................................................................... 114
Table 13: PRBS Generators for BER Analysis ................................................................................................................. 156
Table 14: modulations and input modes ............................................................................................................................ 174
Table 15: connectors allocation, single Ended ECL .......................................................................................................... 174
Table 16: connectors allocation, Differential ECL ............................................................................................................ 175
Table 17: The basic demodulator menus of the CORTEX HDR ....................................................................................... 194
Table 18: The basic test modulator menus of the CORTEX HDR .................................................................................... 196