Safran CORTEX Series - Page 4

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 4
Filtering ................................................................................................................................................... 47 1.6.1.5
Viterbi Convolutional Decoding ............................................................................................................. 48 1.6.1.6
Viterbi ½ .............................................................................................................................................. 48 1.6.1.6.1
Viterbi ¼ .............................................................................................................................................. 48 1.6.1.6.2
De-scrambler ........................................................................................................................................... 49 1.6.1.7
Transport Layer (RS-DVB or asynchronous LDPC layer) ..................................................................... 49 1.6.1.8
BEM 4D 8PSK TCM DVB-S R-S .......................................................................................................... 50 1.6.1.9
VHR-DVB-S2 and CCSDS-SCCC standard ........................................................................................ 50 1.6.1.10
OQPSK/8PSK variable modulation ...................................................................................................... 50 1.6.1.11
Diversity Combining Unit and Antenna Combining .................................................................................. 51 1.6.2
Data Processing Unit ................................................................................................................................. 51 1.6.3
Frame Synchronization ........................................................................................................................... 51 1.6.3.1
Data Time-tagging .................................................................................................................................. 51 1.6.3.2
CRC Frame checking .............................................................................................................................. 51 1.6.3.3
CCSDS and ECSS Decoding .................................................................................................................. 52 1.6.3.4
LDPC Decoding ...................................................................................................................................... 52 1.6.3.5
Data Output ............................................................................................................................................. 52 1.6.3.6
Data Storage .............................................................................................................................................. 53 1.6.4
Playback ..................................................................................................................................................... 54 1.6.5
Test Modulator ........................................................................................................................................... 54 1.6.6
IF Modulation ......................................................................................................................................... 54 1.6.6.1
Noise Source ........................................................................................................................................... 54 1.6.6.2
Modulation .............................................................................................................................................. 54 1.6.6.3
PCM Simulation ...................................................................................................................................... 55 1.6.6.4
Doppler Simulation ................................................................................................................................. 55
1.6.6.5
Start-up Menus ........................................................................................................................................... 55 1.6.7
Frequency Reference .................................................................................................................................. 56 1.6.8
External Reference .................................................................................................................................. 56 1.6.8.1
Internal Reference ................................................................................................................................... 56 1.6.8.2
Time Code Reference ................................................................................................................................. 56 1.6.9
Mechanical - Environment ....................................................................................................................... 56 1.6.10
Supply ....................................................................................................................................................... 57 1.6.11
2 HARDWARE DESCRIPTION .......................................................................................................................... 58
CORTEX HDR INTEGRATION .................................................................................................................. 58 2.1
Hardware Configuration ............................................................................................................................ 58 2.1.1
PC-compatible Workstation ....................................................................................................................... 58 2.1.2
Demodulator board .................................................................................................................................... 59 2.1.3
Overview ................................................................................................................................................. 59 2.1.3.1
Separate IF inputs ................................................................................................................................... 59 2.1.3.2
Test Modulator Board ................................................................................................................................ 60 2.1.4
I/O CONNECTORS DEFINITION ............................................................................................................... 61 2.2
CPU Board I/Os ......................................................................................................................................... 61 2.2.1
Demodulator & Test Modulator I/Os ......................................................................................................... 61 2.2.2
HDR 4G/4G+ I/Os .................................................................................................................................. 61 2.2.2.1
Demodulator I/Os .................................................................................................................................... 62 2.2.2.2
Channel A & Channel B I/Os description ............................................................................................ 65 2.2.2.2.1
AIT Connector (LVDS Data Output - J73) description ....................................................................... 70 2.2.2.2.2
Demodulator inputs description ........................................................................................................... 71 2.2.2.2.3
Test Modulator I/Os ................................................................................................................................ 72 2.2.2.3
Output Data Definition and Timing ........................................................................................................... 73 2.2.3
Timing for all output types...................................................................................................................... 73 2.2.3.1