Xilinx Zynq-7000 - Page 15

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 15
UG586 November 30, 2016
www.xilinx.com
04/24/2012 1.4
• MIG 1.5 release. Updated ISE Design Suite version to 14.1. Updated GUI screen
captures throughout document. Replaced IODELAYCTRL with IDELAYCTRL
throughout.
• Chapter 1: Added I/O Power Reduction option to FPGA Options. Revised I/O
standards for sys_rst option in Bank Selection. Added Creating ISE Project Navigator
Flow for MIG Example Design, Power-Saving Features, Multi-Purpose Register Read
Leveling, OCLKDELAYED Calibration, Upsizing, and External Vref sections. Changed
bits [16:15] to from Rank Count to Reserved in the PHY Control word. Revised
maximum setting of NUM_DQ_PINS in Table 1-11. Revised Figure 1-55 flowchart.
Removed RankSel[1:0] from Figure 1-56 and Figure 1-58. Added mc_odt and mc_cke
to Table 1-87. Replaced AXI Addressing. Updated REFCLK_FREQ, RANK_WIDTH, and
WRLVL in Table 1-92. Added DATA_IO_PRIM_TYPE to Table 1-93. Added bullet about
DQS pins to Bank and Pin Selection Guides for DDR3 Designs. Changed DIFF_SSTL_15
to DIFF_SSTL18_II and SSTL15 to SSTL18_II.
• Chapter 2: Changed DIFF_SSTL_15 to DIFF_HSTL_I and SSTL15 to HSTL_I. Revised I/O
standards for sys_rst option in System Pins Selection. Revised the PHY_BITLANE
parameters in Table 2-11. Added System Clock, PLL Location, and Constraints and
Configuration sections.
• Chapter 3: Changed DIFF_SSTL_15 to DIFF_HSTL_I and SSTL15 to HSTL_I. to Revised
I/O standards for sys_rst option in System Pins Selection. Added the Write
Calibration, System Clock, PLL Location, and Constraints, and Configuration sections.
Revised the PHY_BITLANE parameters in Table 3-15. In Table 3-28, added
dbg_wrcal_sel_stg[1:0], dbg_wrcal[63:0], dbg_wrcal_done[2:0],
dbg_wrcal_po_first_edge[5:0], dbg_wrcal_po_second_edge[5:0], and
dbg_wrcal_po_final[5:0].
01/18/2012 1.3
• MIG 1.4 release. Updated ISE Design Suite version to 13.4. Updated GUI screen
captures throughout document.
• Chapter 1: Added support for DDR2 SDRAM. Added option 3 to MIG Output Options.
Added EDK Clocking. Added Replaced Figure 1-41 and Figure 1-69.
• Chapter 2: Removed Input Clock Period option from Controller Options. Added
Memory Options. Added Reference Clock option to FPGA Options. Updated Debug
Signals.
• Chapter 3: Removed Input Clock Period option from Controller Options. Added Input
Clock Period option to Memory Options. Added Reference Clock option to FPGA
Options. Added Debugging RLDRAM II and RLDRAM 3 Designs.
Date Version Revision
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