Xilinx Zynq-7000 - Page 14

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 14
UG586 November 30, 2016
www.xilinx.com
10/16/2012 1.7
• MIG 1.7 release. Updated ISE Design Suite version to 14.3.
• Chapter 1: Added AXI4-Lite Slave Control/Status Register Interface Block section.
Updated figures (1-32 and 1-37) and added PRBS and Temperature Monitor sections.
Added CLKIN_PERIOD to USE_DM_PORT parameters in Table 1-37. Updated Table
1-38 PHY0_BITLANES description.
• Chapter 2: Added CLKIN_PERIOD to DIVCLK_DIVIDE parameters in Table 2-13.
• Chapter 3: Added RLDRAM 3 content throughout. Updated/added figures (3-10,
3-13, 3-23 to 3-32, 3-36 to 3-37, 3-40 to 3-41, 3-45 to 3-47, and 3-50). Added
mem_ck_lock_complete parameter in Table 3-11. Added CLKOUT0_PHASE parameter
in Table 3-15. Updated descriptions in Table 3-16 and added Table 3-28. Updated
Table 3-29 user_cmd signal. Updated Table 3-31 and 3-34 descriptions. Added
Debugging Write Calibration section.
• Chapter 4: Added System Clock Sharing section
• Chapter 5: Updated figures (5-15, 5-17 to 5-20), updated steps in Getting Started with
Vivado – MIG IP Generation
07/25/2012 1.6
• MIG 1.6 release. Updated ISE Design Suite version to 14.2. Updated GUI screen
captures throughout document.
• Chapter 1: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA
Options, page 36. Changed the parameters nCK_PER_CLK, tZQI, SYSCLK_TYPE,
REFCLK_TYPE, and APP_DATA_WIDTH. Added bulleted item about multiple CK
outputs to Bank and Pin Selection Guides for DDR3 Designs, page 186. Updated Trace
Lengths, page 191 and Termination, page 200.
• Chapter 2: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA
Options, page 282. Changed the parameters SYSCLK_TYPE and REFCLK_TYPE.
• Chapter 3: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA
Options, page 282. Changed the parameters SYSCLK_TYPE and REFCLK_TYPE.
• Chapter 6: Added new chapter on migrating to Vivado Design Suite.
06/13/2012 1.5
Revised the recommended total electrical delay on CK/CK# relative to DQS/DQS# on
page 191.
Date Version Revision
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