Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 13
UG586 November 30, 2016
www.xilinx.com
12/18/2012 1.8
• ISE 14.4 and Vivado 2012.4 Design Suite releases for MIG v1.8.
Chapter 1
• Updated Table 1-2 to 1-9 with new table note and.v name.
• Updated Fig. 1-16 FPGA Options GUI.
• Added XADC Instantiation bullet.
• Added description to sim.do in Table 1-4.
• Updated Table 1-11 DATA_PATTERN to 0xA.
• Updated Table 1-13 vio_data_mode_value[3:0] to 0xA.
• Updated description in Setting Up for Simulation.
• Added description to EDK Clocking.
• Updated ui_clk and ui_clk_sync_rst in Table 1-17.
• Added description in Internal (FPGA) Logic Clock.
• Added TEMP_MON_CONTROL to Table 1-91.
• Added DATA_IO_IDLE_PWRDWN and CA_MIRROR to Table 1-92.
• Added HP bank description in Bank and Pin Selection Guides for DDR3 Designs.
• Added DDR3 SDRAM interface description to Configuration.
• Added HP bank description in Bank and Pin Selection Guides for DDR2 Designs.
• Added DDR2 SDRAM interface description to Configuration.
Chapter 2
• Updated Table 2-2 and 2-7 to 2-8 with new table note and.v name.
• Added description to sim.do in Table 2-3.
• Updated descriptions and added Fig 2-26 to Clocking Architecture.
• Updated description in Write Path Output Architecture.
• Updated descriptions in Trace Length Requirements.
• Added QDRII description in Configuration.
• Added description to Verifying the Simulation Using the Example Design.
• Added Margin Check and Automated Margin Check sections.
Chapter 3
• Updated Table 3-2 and 3-6 to 3-8 with new table note and.v name.
• Added description to sim.do in Table 3-3.
• Updated Table 3-10 DATA_PATTERN to 0xA.
• Updated descriptions and added Fig 3-30 to Clocking Architecture.
• Updated descriptions in Trace Length Requirements.
• Added descriptions in RLDRAM II.
• Added RLDRAM II description in Configuration.
• Added description to Verifying the Simulation Using the Example Design.
• Added Debug section.
Date Version Revision
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