Xilinx Zynq-7000 - Page 12

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 12
UG586 November 30, 2016
www.xilinx.com
Continued
Chapter 2
• Added No Buffer option description in FPGA Options section.
• Added pinout description in Verify Pin Changes and Update Design section.
• Updated Fig. 2-15 FPGA Options.
• Updated REFCLK_FREQ and RST_ACT_LOW in Table 2-13 7 Series FPGAs QDR II+
SRAM Memory Interface Solution Configurable Parameters
• Updated Table 2-14 QDR II+ SRAM Memory Interface Solution Pinout Parameters.
• Added description in Verifying the Simulation Using the Example Design section.
Chapter 3
• Added No Buffer option description in FPGA Options section.
• Updated Fig. 3-14 FPGA Options.
• Added Verify Pin Changes and Update Design section.
• Updated nCK_PER_CLK in Table 3-10 Traffic Generator Parameters Set in the
example_top Module
• Updated Table 3-15 RLDRAM II Memory Interface Solution Configurable Parameters.
• Updated Table 3-16 RLDRAM II Memory Interface Solution Pinout Parameters.
• Added description in Verifying the Simulation Using the Example Design section.
Chapter 4
• Added new LPDDR2 SDRAM section.
Chapter 6
• Updated to new GUIs.
Date Version Revision
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