Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 11
UG586 November 30, 2016
www.xilinx.com
Continued
• Updated Table 3-27 DEBUG_PORT Signal with
dbg_rd_stage1_rtr_error[N_DATA_LANES - 1:0] and
dbg_rd_stage1_error[N_DATA_LANES - 1:0].
• Updated Tables 3-31 and 3-32 Read Stage 1 and Stage 2 Debug Signal Map tables.
• Added Fig. 3-36 Calibration Flow Diagram and Fig. 3-37 Read Level Stage 1.
• Added description to Data Alignment and Valid Generation section.
• Updated description and added Figs. 3-38 to 3-43 in Write Calibration section.
• Added Write Calibration Debug Map section.
Chapter 4
• Updated ChipScope to Vivado logic analyzer, VIO, and ILA.
• Updated ui_clk and ui_clk_sync_rst descriptions in Table 4-14 User Interface.
• Updated ui_clk and ui_clk_sync_rst descriptions.
• Added Ordering Modes in Reordering section and added modes in Table 4-25.
• Added DM in DQ descriptions.
• Added Termination description in LPDDR2 Pinout Examples section.
Chapter 6
• Added Upgrading the ISE/CORE Generator MIG Core in Vivado section.
03/20/2013 1.9
• ISE 14.5 and Vivado Design Suite 2013.1 releases for MIG v1.9 and v1.9a.
Chapter 1
• Added Memory Part frequency in Controller Options section.
• Added No Buffer option description in FPGA Options section.
• Added pinout description in Verify Pin Changes and Update Design section.
• Updated Fig. 1-15 Setting Memory Mode Options.
• Updated Fig. 1-16 FPGA Options.
• Updated Fig. 1-30 7 Series FPGAs Memory Interface Solution to User’s FPGA Logic
• Added ECC description in AXI4 Slave Interface Block section.
• Updated Table 1-91 7 Series FPGA Memory Solution Configuration Parameters.
• Updated Table 1-92 Embedded 7 Series FPGAs Memory Solution Configuration
Parameters.
• Updated Table 1-93 DDR2/DDR3 SDRAM Memory Interface Solution Pinout
Parameters.
• Added description in Verifying the Simulation Using the Example Design section.
• Reworked Design Guidelines DDR3 SDRAM section.
• Added new debug section.
Date Version Revision
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