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Xilinx Zynq-7000

Xilinx Zynq-7000
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 10
UG586 November 30, 2016
www.xilinx.com
06/19/2013 2.0
Vivado Design Suite release only for MIG v2.0. Revision number advanced to 2.0 to
align with core version number.
Chapter 1
Updated ChipScope to Vivado logic analyzer, VIO, and ILA.
Updated ui_clk and ui_clk_sync_rst descriptions in Table 1-17 User Interface.
Updated ui_clk and ui_clk_sync_rst descriptions.
Added Ordering Modes in Reordering section and added modes in Table 1-91.
Updated ECC enable in AXI4 Slave Interface Block section.
Updated Read Priority (RD_PRI) section.
Updated Table 1-19 AXI4 Slave Interface Parameters, C_S_AXI_ADDR_WIDTH value
and descriptions.
Added Write Priority description.
Updated PHASER_IN DQSFOUND Calibration section.
•Removed Downsizing Option.
Added DM in DQ descriptions.
Added Dynamic Calibration and Periodic Read Behavior section.
Added Vivado Lab Tools section.
Added AR 54025 for Vivado.
Updated Debugging PHASER_IN DQSFOUND Calibration Failures
(dbg_pi_dqsfound_err = 1) section.
Chapter 2
Updated ChipScope to Vivado logic analyzer, VIO, and ILA.
Added Fixed Latency Mode description in Controller Options section.
Removed qdr_qvld in Table 2-12 Physical Interface Signals.
Updated Figure 2-26 Four-Word Burst Length Memory Device Protocol.
Updated Output Architecture section in Write Path.
Added Write Calibration section.
•Removed QVLD.
Updated Table 2-20 Write Init Debug Signal Map.
Updated Tables 2-21 and 2-22 Read Stage 1 and Stage 2 Debug Signal Map tables.
Chapter 3
Updated ChipScope to Vivado logic analyzer, VIO, and ILA.
Removed rld_qvld in Table 3-13 Physical Interface Signals.
Removed QVLD and QVLD_MAP in Table 3-16 RLDRAM II Memory Interface Solution
Pinout Parameters.
•Removed QVLD.
Updated descriptions in Manual Pinout Changes section.
Added new calibration description in Calibration section.
Updated Table 3-26 Physical Layer Simple Status Bus Description Defined in the
rld_phy_top Module.
Date Version Revision
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