Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 9
UG586 November 30, 2016
www.xilinx.com
10/02/2013 2.0
• Vivado Design Suite release only for MIG v2.0.
• Removed ISE content throughout book and updated screenshots to v2.0.
Chapter 1
• Updated Memory Part bullet description.
• Updated Table 1-4 sim.do description and simulation directory.
• Updated Fig. 1-44 7 Series FPGAs MIS.
• Added aresetn in Table 1-20 AXI4 Slave Interface Signals.
• Added Caution note in Single Error and Double Error Reporting section.
• Updated Table 1-77 Memory Interface Commands.
• Updated and added stage 3 tap in OCLKDELAYED Calibration section.
• Added #4 table note to Table 1-91 7 Series FPGA Memory Solution Configuration
Parameters.
• Updated description in app_wdf_mask[APP_MASK_WIDTH - 1:0] section.
• Added Memory Address Mapping description in User Interface section.
• Updated Table 1-106 Debug Signals of Interest for OCLKDELAYED Calibration
Chapter 2
• Updated Table 2-3 sim.do description and simulation directory.
• Updated DIFF_HSTL_I in I/O Standards table.
• Updated reference clock descriptions in Clocking Architecture section.
• Added #1 table note to Table 2-11 7 Series FPGAs QDR II+ SRAM Memory Interface
Solution Configurable Parameters. And updated SIM_BYPASS_INIT_CAL.
Chapter 3
• Updated Table 3-3 sim.do description and simulation directory.
• Updated reference clock descriptions in Clocking Architecture section.
• Added #1 table note to Table 3-13 RLDRAM II Memory Interface Solution
Configurable Parameters. And updated SIM_BYPASS_INIT_CAL.
Chapter 4
• Updated Table 4-4 sim.do description and simulation directory.
• Updated Fig. 4-37 7 Series FPGAs MIS.
• Updated Table 4-14 User Interface.
• Added #4 note to Table 4-25 7 Series FPGA Memory Solution Configuration
Parameters.
• Updated description in app_wdf_mask[APP_MASK_WIDTH - 1:0] section.
• Added Memory Address Mapping description in User Interface section.
Date Version Revision
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