Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 151
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
The stage 3 start tap value places the DQS anywhere between 90° and 225° with respect to
DQ. The number of edges detected depends on the write level taps value after the initial
write leveling and the starting DQS position with respect to DQ. If DQS starts in the rise DQ
window between 90° and 180°, then the following can occur:
• Either f2z, z2f, and f2o edges can be detected
• Or f2z and z2f edges of the rise window can be detected
• Or only f2z edge can be detected or only z2f edge can be detected
If DQS starts in the noise/jitter region around 180°, then the following can occur:
• Either z2f, f2o, and o2f edges can be detected
• Or f2z, z2f and f2o edges can be detected
• Or z2f and f2o edges of the noise can be detected
Finally, if DQS starts in the fall window between 180° and 225°, then the following can occur:
• Either z2f, f2o, and o2f edges can be detected
• Or f2o and o2f edges can be detected
• Or only f2o edge can be detected
Table 1-60 describes the different starting scenarios of write DQS with respect to DQ, the
possible edges that can be detected, and the equation used to determine the center value.
X-Ref Target - Figure 1-66
Figure 1-66: Rise and Fall Write Data Window Edges
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Table 1-60: Starting Scenarios for Write DQS
Start DQS f2z z2f f2o o2f Center Equation
Rise Window (90
o
to 180
o
)
Case 1 Found Found Found
Not
Found
(fuzz2zero + zero2fuzz)/2
Case 2 Found Found
Not
Found
Not
Found
(fuzz2zero + zero2fuzz)/2
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English