Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 153
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-68 shows an initial DQS to CK alignment case for component interfaces. The
assumption is that component interfaces also use the fly-by topology, thereby requiring
write leveling.
The PHASER_OUT fine and coarse delay provides 1 t
CK
worth of delay for write leveling. The
additional clock cycle of delay required to align to the correct CK edge is achieved using the
coarse delay line. If the total delay required is over one clock cycle, the div_cycle_delay
input to the PHASER_OUT block need not be asserted because a circular buffer was added
to the PHASER_OUT block.
X-Ref Target - Figure 1-67
Figure 1-67: UDIMM/RDIMM DQS-to-CK Initial Alignment
5'?C??
#+ #OMP
7RITELEVELED$13
COMPONECYCLE
EARLIERTHAN
7R?#MD#+
EDGESO$13$1
REQUIRESANADDITIONAL
CYCLEOFDELAY
PS
PS
#+EDGETHATCLOCKS7R?#MD
$13 #OMP
BEFOREWRITELEVELING
7RITELEVELED
$13 #OMP
ALIGNEDWITH
WRITECOMMAND#+
#+ #OMP
$13 #OMP
BEFOREWRITELEVELING
X-Ref Target - Figure 1-68
Figure 1-68: Component DQS-to-CK Initial Alignment
5'?C??
#+ #OMP
$13 #OMP
7RITELEVELED$13
#OMPONECYCLE
AFTERTHE7R?#MD#+
EDGESO$13$1MUST
BESENTOUT#7,
AFTERTHE7R?#MD
PS
#+EDGETHATCLOCKS7R?#MD
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