Xilinx Zynq-7000 - Page 176

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 176
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
X-Ref Target - Figure 1-88
Figure 1-88: PHY Interface Example
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