Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 177
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
The data offset field (MC_DATA_OFFSET) in the PHY control word for read commands is
determined during PHASER_IN DQSFOUND calibration. It is provided by the PHY through
the PHY interface. The Memory Controller must add the slot number being used to this read
data offset value provided by the PHY. PHY control inside the PHY needs to know when to
read data from IN_FIFO after a READ command has been issued to memory.
Read data offset = Calibrated PHY read data offset + slot number
The data offset field in the PHY control word for write commands must be set based on the
slot number being used, CWL, and the nCK_PER_CLK parameter value as shown in the
following equations:
•For nCK_PER_CLK = 4
Write data offset = CWL + 2 + slot number
•For nCK_PER_CLK = 2
Write data offset = CWL – 2 + slot number
The write waveform shown in Figure 1-89 illustrates an example with DDR3 SDRAM CWL =
7 and nCK_PER_CLK = 4. The selected slot number can be 1 or 3.
Write data offset = CWL + slot number + 2
= 7 + 1 + 2 = 10
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