Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 186
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
DATA_IO_PRIM_TYPE
This option instantiates IBUF primitives for
Data (DQ) and Strobe (DQS) as per banks
selected for the interface and also depends
on the I/O Power Reduction option in the
MIG tool.
“HP_LP”
“HR_LP”
“DEFAULT”
DATA_IO_IDLE_PWRDWN
This option is set to ON valid when I/O
Power reduction option is enabled.
"ON," "OFF”
CA_MIRROR
This option enables Address mirroring on
second rank when it is enabled. This is valid
for DDR3 SDRAM dual rank UDIMMs only.
This parameter should not be changed.
"ON," "OFF”
SYSCLK_TYPE
This parameter indicates whether the
system uses single-ended system clocks,
differential system clocks, or is driven from
an internal clock (No Buffer). Based on the
selected CLK_TYPE, the clocks must be
placed on the correct input ports. For
differential clocks, sys_clk_p/sys_clk_n must
be used. For single-ended clocks, sys_clk_i
must be used. For the No Buffer option,
sys_clk_i, which appears in port list, needs to
be driven from an internal clock.
DIFFERENTIAL
SINGLE_ENDED
NO_BUFFER
REFCLK_TYPE
This parameter indicates whether the
system uses single-ended reference clocks,
differential reference clocks, is driven from
an internal clock (No Buffer), or can connect
system clock inputs only (Use System Clock).
Based on the selected CLK_TYPE, the clocks
must be placed on the correct input ports.
For differential clocks, clk_ref_p/clk_ref_n
must be used. For single-ended clocks,
clk_ref_i must be used. For the No Buffer
option, clk_ref_i, which appears in the port
list, needs to be driven from an internal
clock. For the Use System Clock option,
clk_ref_i is connected to the system clock in
the user design top module.
DIFFERENTIAL
SINGLE_ENDED
NO_BUFFER
USE_SYSTEM_CLOCK
CLKIN_PERIOD – Input clock period.
CLKFBOUT_MULT –
PLL voltage-controlled oscillator
(VCO) multiplier. This value is set by
the MIG tool based on the
frequency of operation.
CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE
–
VCO output divisor for PLL outputs.
This value is set by the MIG tool
based on the frequency of
operation.
Table 1-65: Embedded 7 Series FPGAs Memory Solution Configuration Parameters (Cont’d)
Parameter Description Options
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